{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,27]],"date-time":"2025-11-27T06:26:41Z","timestamp":1764224801273,"version":"3.32.0"},"reference-count":16,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2005,12,1]],"date-time":"2005-12-01T00:00:00Z","timestamp":1133395200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2005,12]]},"DOI":"10.1007\/s10836-005-2911-4","type":"journal-article","created":{"date-parts":[[2005,11,17]],"date-time":"2005-11-17T18:29:36Z","timestamp":1132252176000},"page":"599-611","source":"Crossref","is-referenced-by-count":23,"title":["Multiple-Constraint Driven System-on-Chip Test Time Optimization"],"prefix":"10.1007","volume":"21","author":[{"given":"Julien","family":"Pouget","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Erik","family":"Larsson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zebo","family":"Peng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"2911_CR1","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1109\/92.585217","volume":"5","author":"R.M. Chou","year":"1997","unstructured":"R.M. Chou, K.K. Saluja, and V.D. Agrawal, \u201cScheduling Tests for VLSI Systems Under Power Constraints,\u201d IEEE Transactions on VLSI Systems, vol. 5, no. 2, pp. 175\u2013185, 1997.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"2911_CR2","doi-asserted-by":"crossref","unstructured":"E. Cota, L. Cairo, M. Lubaszewski, and A. Orailoglu, \u201cTest Planning and Design Space Exploration in a Core-based Environment,\u201d in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Paris, France, 2002, pp. 478\u2013485.","DOI":"10.1109\/DATE.2002.998316"},{"key":"2911_CR3","unstructured":"H-S Hsu, J-R Huang, K-L Cheng, C-W Wang, C-T Huang, and C-W Wu, \u201cTest Scheduling and Test Access Architecture Optimization for System-on-Chip,\u201d in Proceedings of IEEE Asian Test Symposium (ATS), Tamuning, Guam, USA, 2002, pp. 411\u2013416."},{"key":"2911_CR4","doi-asserted-by":"crossref","unstructured":"Y. Huang, S.M. Reddy, W-T Cheng, P. Reuter, N. Mukherjee, C-C Tsai, O. Samman, and Y. Zaidan, \u201cOptimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm,\u201d in Proceedings IEEE of International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 74\u201382.","DOI":"10.1109\/TEST.2002.1041747"},{"key":"2911_CR5","doi-asserted-by":"crossref","unstructured":"V. Iyengar, K. Chakrabarty, and E.J. Marinissen, \u201cTest Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip,\u201d Journal of Electronic Testing; Theory and Applications (JETTA), pp. 213\u2013230, 2002.","DOI":"10.1007\/978-1-4615-1113-7_4"},{"key":"2911_CR6","doi-asserted-by":"crossref","unstructured":"V. Iyengar K. Chakrabarty, and E.J. Marinissen, \u201cEfficient Wrapper\/TAM Co-Optimization for Large SOCs,\u201d in Proceedings of Design and Test in Europe (DATE), Paris, France, 2002, pp. 491\u2013498.","DOI":"10.1109\/DATE.2002.998318"},{"key":"2911_CR7","doi-asserted-by":"crossref","unstructured":"V. Iyengar, K. Chakrabarty, and E.J. Marinissen, \u201cOn Using Rectangle Packing for SOC Wrapper\/TAM Co-Optimization,\u201d in Proceedings of IEEE VLSI Test Symposium (VTS), Monterey, California, USA, 2002, pp. 253\u2013258.","DOI":"10.1109\/VTS.2002.1011146"},{"key":"2911_CR8","doi-asserted-by":"crossref","unstructured":"V. Iyengar, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, \u201cTest Resource Optimization for Multi-Site Testing of SOCs under ATE Memory Depth Constraints,\u201d in Proceedings of IEEE International Test Conference, Baltimore, MD, USA, 2002, pp. 1159\u20131168.","DOI":"10.1109\/TEST.2002.1041874"},{"key":"2911_CR9","doi-asserted-by":"crossref","unstructured":"V. Iyengar, K. Chakrabarty, M.D. Krasniewski, and G.N. Kuma, \u201cDesign and Optimization of Multi-level TAM Architectures for Hierarchical SOCs,\u201d in Proceedings of IEEE VLSI Test Symposium (VTS), 2003, pp. 299\u2013304.","DOI":"10.1109\/VTEST.2003.1197667"},{"key":"2911_CR10","doi-asserted-by":"crossref","unstructured":"S.K. Goel and E.J. Marinissen, \u201cCluster-Based Test Architecture Design for System-On-Chip,\u201d in Proceedings of IEEE VLSI Test Symposium (VTS), Monterey, California, USA, 2002, pp. 259\u2013264.","DOI":"10.1109\/VTS.2002.1011147"},{"key":"2911_CR11","doi-asserted-by":"crossref","unstructured":"S.K. Goel and E.J. Marinissen, \u201cEffective and efficient test architecture design for SOCs,\u201d in Proceedings of IEEE International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 529\u2013538.","DOI":"10.1109\/TEST.2002.1041803"},{"key":"2911_CR12","doi-asserted-by":"crossref","unstructured":"S. Koranne, \u201cOn Test Scheduling for Core-based. SOCs,\u201d in Proceedings of International Conference on VLSI Design, Bangalore, India, 2002, pp 505\u2013510.","DOI":"10.1109\/ASPDAC.2002.994970"},{"key":"2911_CR13","doi-asserted-by":"crossref","unstructured":"S. Koranne and V. Iyengar, \u201cOn the use of k - tuples for SoC test schedule representation,\u201d in Proceedings of International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 539\u2013548.","DOI":"10.1109\/TEST.2002.1041804"},{"key":"2911_CR14","doi-asserted-by":"crossref","unstructured":"E.J. Marinissen, R. Kapur, and Y. Zorian, \u201cOn Using IEEE P1500 SECT for Test Plug-n-play,\u201d in Proceedings of IEEE International Test Conference (ITC), Atlantic City, NJ, USA, 2000, pp. 770\u2013777.","DOI":"10.1109\/TEST.2000.894273"},{"key":"2911_CR15","doi-asserted-by":"crossref","unstructured":"J. Pouget, E. Larsson, Z. Peng, M.-L. Flottes, and B. Rouzeyre, \u201cAn Efficient Approach to SoC Wrapper Design, TAM configuration, and Test Scheduling,\u201d in Proceedings of IEEE European Test Workshop (ETW), Maastricht, The Nederlands, 2003, pp. 117-122.","DOI":"10.1109\/ETW.2003.1231668"},{"key":"2911_CR16","doi-asserted-by":"crossref","unstructured":"J. Pouget, E. Larsson, and Z. Peng, \u201cSOC Test Time Minimization Under Multiple Constraints,\u201d in Proceedings of Asian Test Symposium (ATS), Xian, China, 2003, pp. 312\u2013317.","DOI":"10.1109\/ATS.2003.1250829"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-2911-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-005-2911-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-2911-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,5]],"date-time":"2025-01-05T18:17:22Z","timestamp":1736101042000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-005-2911-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,12]]},"references-count":16,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2005,12]]}},"alternative-id":["2911"],"URL":"https:\/\/doi.org\/10.1007\/s10836-005-2911-4","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2005,12]]}}}