{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,23]],"date-time":"2024-12-23T10:40:13Z","timestamp":1734950413305,"version":"3.32.0"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2005,2,1]],"date-time":"2005-02-01T00:00:00Z","timestamp":1107216000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2005,2]]},"DOI":"10.1007\/s10836-005-5287-6","type":"journal-article","created":{"date-parts":[[2005,2,14]],"date-time":"2005-02-14T15:20:11Z","timestamp":1108394411000},"page":"57-69","source":"Crossref","is-referenced-by-count":7,"title":["Modeling Feedback Bridging Faults with Non-Zero Resistance"],"prefix":"10.1007","volume":"21","author":[{"given":"Ilia","family":"Polian","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Piet","family":"Engelke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michel","family":"Renovell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bernd","family":"Becker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"7","key":"CR1","doi-asserted-by":"crossref","first-page":"658","DOI":"10.1109\/TC.1985.1676604","volume":"C-34","author":"M. Abramovici","year":"1983","unstructured":"M. Abramovici and P. Menon, ?A Practical Approach to Fault simulation and Test Generation for Bridging Faults,? IEEE Trans. on Comp., vol. C-34, no. 7, pp. 658?663, 1983.","journal-title":"IEEE Trans. on Comp."},{"issue":"5","key":"CR2","doi-asserted-by":"crossref","first-page":"312","DOI":"10.1109\/TCAD.1985.1270127","volume":"4","author":"P. Banerjee","year":"1985","unstructured":"P. Banerjee and J.A. Abraham, ?A Multivalued Algebra for Modeling PhysicalFailures in MOS VLSI Circuits,? IEEE Trans. on CAD, vol. 4, no. 5, pp. 312?321, 1985.","journal-title":"IEEE Trans. on CAD"},{"issue":"3","key":"CR3","doi-asserted-by":"crossref","first-page":"338","DOI":"10.1109\/12.660170","volume":"47","author":"B. Chess","year":"1998","unstructured":"B. Chess and T. Larrabee, ?Logic Testing of Bridging Faults in CMOS Integrated Circuits,? IEEE Trans. on Comp., vol. 47, no. 3, pp. 338?345, 1998.","journal-title":"IEEE Trans. on Comp."},{"key":"CR4","doi-asserted-by":"crossref","unstructured":"J.P. Cusey and J.H. Patel, ?BART: A Bridging Fault Test Generator for Sequential Circuits,? in Int?l Test Conf., 1997, pp. 838?847.","DOI":"10.1109\/TEST.1997.639698"},{"key":"CR5","doi-asserted-by":"crossref","unstructured":"P. Dahlgren, ?Switch-Level Bridging Fault Simulation in the Presence of Feedbacks,? in Int?l Test Conf., 1998, pp. 363?371.","DOI":"10.1109\/TEST.1998.743175"},{"key":"CR6","doi-asserted-by":"crossref","unstructured":"P. Engelke, I. Polian, M. Renovell, and B. Becker, ?Simulating Resistive Bridging and Stuck-At Faults,? in Int?l Test Conf., 2003, pp.~1051?1059.","DOI":"10.1109\/TEST.2003.1271093"},{"issue":"8","key":"CR7","doi-asserted-by":"crossref","first-page":"941","DOI":"10.1109\/TCAD.2002.800457","volume":"21","author":"M. Favalli","year":"2002","unstructured":"M. Favalli and M. Dalpasso, ?Bridging Fault Modeling and Simulation for Deep Submicron CMOS ICs,? IEEE Trans. on CAD, vol. 21, no. 8, pp. 941?953, 2002.","journal-title":"IEEE Trans. on CAD"},{"key":"CR8","doi-asserted-by":"crossref","unstructured":"M. Favalli, M. Dalpasso, P. Olivo, and B. Ricco, ?Analysis of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs,? in Int?l Test Conf., 1993, pp.~865?873.","DOI":"10.1109\/TEST.1992.527858"},{"key":"CR9","doi-asserted-by":"crossref","unstructured":"F. Ferguson and T. Larrabee, ?Test Pattern Generation for Realistic Bridge Fault in CMOS ICs,? in Int?l Test Conf., 1991, pp. 492?499.","DOI":"10.1109\/TEST.1991.519711"},{"key":"CR10","doi-asserted-by":"crossref","unstructured":"F.J. Ferguson and J. Shen, ?Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis,? in Int?l Test Conf., 1988, pp. 475?484.","DOI":"10.1109\/TEST.1988.207759"},{"key":"CR11","doi-asserted-by":"crossref","unstructured":"G. Greenstein and J. Patel, ?E-PROOFS: A CMOS Bridging Fault Simulator,? in Int?l Conf. on CAD., 1992, pp. 268?271.","DOI":"10.1109\/ICCAD.1992.279362"},{"key":"CR12","unstructured":"H. Hao and E. McCluskey, ?Resistive Shorts Within CMOS Gates,? in Int?l Test Conf., 1991, pp. 292?301."},{"key":"CR13","unstructured":"C. Lee and D.M.H. Walker, ?PROBE: A PPSFP Simulator for Resistive Bridging Faults,? in VLSI Test Symp., 2000, pp. 105?110."},{"key":"CR14","doi-asserted-by":"crossref","unstructured":"S. Ma, I. Shaik, and R. Scott-Fetherston, ?A Comparison of Bridging Fault Simulation Methods,? in Int?l Test Conf., 1999, pp. 587?595.","DOI":"10.1109\/TEST.1999.805783"},{"key":"CR15","doi-asserted-by":"crossref","unstructured":"T. Maeda and K. Kinoshita, ?Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits,? in Int?l Test Conf., 2000, pp.~510?519.","DOI":"10.1109\/TEST.2000.894244"},{"key":"CR16","unstructured":"Y. Malaiya, A. Jayasumana, and R. Rajsuman, ?A Detailed Examination of Bridging Faults,? in Int?l Conf. on Comp. Design., 1986, pp. 78?81."},{"key":"CR17","doi-asserted-by":"crossref","unstructured":"P. Maxwell and R. Aitken, ?Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds,? in Int?l Test Conf., 1993, pp. 63?72.","DOI":"10.1109\/TEST.1993.470717"},{"issue":"7","key":"CR18","doi-asserted-by":"crossref","first-page":"720","DOI":"10.1109\/T-C.1974.224020","volume":"C-23","author":"K.C.Y. Mei","year":"1974","unstructured":"K.C.Y. Mei, ?Bridging and Stuck-At Faults,? IEEE Trans. on Comp., vol. C-23, no. 7, pp. 720?727, 1974.","journal-title":"IEEE Trans. on Comp."},{"key":"CR19","doi-asserted-by":"crossref","unstructured":"S. Millman and S.J. Garvey, ?An Accurate Bridging Fault Test Pattern Generator,? in Int?l Test Conf., 1991, pp. 411?418.","DOI":"10.1109\/TEST.1991.519701"},{"key":"CR20","doi-asserted-by":"crossref","unstructured":"I. Polian, P. Engelke, and B. Becker, ?Efficient Bridging Fault Simulationof Sequential Circuits Based on Multi-Valued Logics,? in Int?l Symp. on Multi-Valued Logic., 2002, pp. 216?222.","DOI":"10.1109\/ISMVL.2002.1011092"},{"key":"CR21","doi-asserted-by":"crossref","unstructured":"J. Rearick and J. Patel, ?Fast and Accurate CMOS Bridging Fault Simulation,? in Int?l Test Conf., 1993, pp. 54?62.","DOI":"10.1109\/TEST.1993.470718"},{"key":"CR22","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1023\/A:1008336919671","volume":"14","author":"M. Renovell","year":"1999","unstructured":"M. Renovell, F. Aza\u00efs, and Y. Bertrand, ?Detection of Defects Using Fault Model Oriented Test Sequences,? Jour. of Electronic Testing: Theory and Applications, vol. 14, pp. 13?22, 1999.","journal-title":"Jour. of Electronic Testing: Theory and Applications"},{"key":"CR23","doi-asserted-by":"crossref","unstructured":"M. Renovell, P. Huc, and Y. Bertrand, ?CMOS Bridge Fault Modeling,? in VLSI Test Symp., 1994, pp. 392?397.","DOI":"10.1109\/VTEST.1994.292283"},{"key":"CR24","doi-asserted-by":"crossref","unstructured":"M. Renovell, P. Huc, and Y. Bertrand, ?The Concept of Resistance Interval: A New Parametric Model for Resistive Bridging Fault,? in VLSI Test Symp., 1995, pp. 184?189.","DOI":"10.1109\/VTEST.1995.512635"},{"key":"CR25","doi-asserted-by":"crossref","unstructured":"R. Rodr\u00edguez-Monta\u00f1\u00e9s, E. Bruls, and J. Figueras, ?Bridging Defects Resistance Measurements in a CMOS Process,? in Int?l Test Conf., 1992, pp. 892?899.","DOI":"10.1109\/TEST.1992.527915"},{"key":"CR26","doi-asserted-by":"crossref","unstructured":"M.B. Santos, and J.P. Teixeira, ?Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL,? in Design, Automation and Test in Europe, 1999.","DOI":"10.1145\/307418.307562"},{"key":"CR27","doi-asserted-by":"crossref","unstructured":"V. Sar-Dessai and D. Walker, ?Accurate Fault Modeling and Fault Simulation of Resistive Bridges,? in Int. Symp. Defect and Fault Tolerance in VLSI Systems, 1998, pp. 102?107.","DOI":"10.1109\/DFTVS.1998.732156"},{"key":"CR28","doi-asserted-by":"crossref","unstructured":"V. Sar-Dessai and D. Walker, ?Resistive Bridge Fault Modeling, Simulation and Test Generation,? in Int?l Test Conf., 1999, pp. 596?605.","DOI":"10.1109\/TEST.1999.805784"},{"key":"CR29","doi-asserted-by":"crossref","unstructured":"H. Vierhaus, W. Meyer, and U. Glaser, ?CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects,? in Int?l Test Conf., 1993, pp. 83?91.","DOI":"10.1109\/TEST.1993.470715"},{"key":"CR30","doi-asserted-by":"crossref","unstructured":"L.-C. Wang, M.R. Mercer, and T. Williams, ?Using Target Faults To Detect Non-Target Faults,? in Int?l Test Conf., 1996, pp. 629?638.","DOI":"10.1109\/TEST.1996.557120"},{"key":"CR31","unstructured":"S. Xu and S. Su, ?Testing Feedback Briging Faults Among Internal, Input and Output Lines by Two Patterns,? in Int?l Conf. on Circuits and Computers, 1982, pp. 214?217."},{"issue":"6","key":"CR32","doi-asserted-by":"crossref","first-page":"553","DOI":"10.1109\/TC.1985.5009408","volume":"C-34","author":"S. Xu","year":"1985","unstructured":"S. Xu and S. Su, ?Detecting I\/O and Internal Feedback Bridging Faults,? IEEE Trans. on Comp., vol. C-34, no. 6, pp. 553?557, 1985.","journal-title":"IEEE Trans. on Comp."},{"key":"CR33","doi-asserted-by":"crossref","unstructured":"S. Zachariah, S. Chakravarty, and C. Roth, ?A Novel Algorithm to Extract Two-Node Bridges,? in Design Automation Conf., 2000, pp. 790?793.","DOI":"10.1145\/337292.337780"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-5287-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-005-5287-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-5287-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,23]],"date-time":"2024-12-23T09:42:00Z","timestamp":1734946920000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-005-5287-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,2]]},"references-count":33,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2005,2]]}},"alternative-id":["5287"],"URL":"https:\/\/doi.org\/10.1007\/s10836-005-5287-6","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2005,2]]}}}