{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T23:04:33Z","timestamp":1648767873077},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2005,2,1]],"date-time":"2005-02-01T00:00:00Z","timestamp":1107216000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2005,2]]},"DOI":"10.1007\/s10836-005-5288-5","type":"journal-article","created":{"date-parts":[[2005,2,14]],"date-time":"2005-02-14T10:20:11Z","timestamp":1108376411000},"page":"71-82","source":"Crossref","is-referenced-by-count":2,"title":["A New Testability Calculation Method to Guide RTL Test Generation"],"prefix":"10.1007","volume":"21","author":[{"given":"Jaan","family":"Raik","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tanel","family":"N\ufffdmmeots","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raimund","family":"Ubar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"CR1","volume-title":"Design of Testable Logic Circuits","author":"R.G. Bennetts","year":"1984","unstructured":"R.G. Bennetts, Design of Testable Logic Circuits, London: Addison-Wesley Publishing Company, 1984."},{"key":"CR2","volume-title":"Essentials of Electronic Testing","author":"M.L. Bushnell","year":"2000","unstructured":"M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing, Boston Dordrecht London: Kluwer Academic Publishers, 2000."},{"issue":"6","key":"CR3","doi-asserted-by":"crossref","first-page":"777","DOI":"10.1109\/43.285251","volume":"13","author":"C.-H. Chen","year":"1994","unstructured":"C.-H. Chen, T. Karnik, and D.G. Saab, ?Structural and Behavioral Synthesis for Testability Techniques?, IEEE Trans. on CAD, vol. 13 no. 6, pp. 777?785, 1994.","journal-title":"IEEE Trans. on CAD"},{"key":"CR4","unstructured":"F. Corno, P. Prinetto, and M. Sonza Reorda, ?BELT\u00c0: A Tool for Handling Testability at the System Level?, IEEE European Test Workshop, May 1996."},{"key":"CR5","doi-asserted-by":"crossref","unstructured":"M.L. Flottes, R. Pires, and B. Rouzeyre, ?Analyzing Testability from Behavioral to RT Level?, in Proc. European Design & Test Conf., 1997, pp. 159?165.","DOI":"10.1109\/EDTC.1997.582352"},{"key":"CR6","doi-asserted-by":"crossref","unstructured":"F. Corno, P. Prinetto, and M. Sonza Reorda, ?Testability Analysis and ATPG on Behavioral RT-Level VHDL?, in Proc. Int. Test Conf, 1997, pp. 753?759.","DOI":"10.1109\/TEST.1997.639688"},{"key":"CR7","doi-asserted-by":"crossref","unstructured":"L.H. Goldstein, ?SCOAP: Sandia Controllability Observability Analysis Program,? in Proc. of Design Automation Conf., June 1980, pp. 190?196.","DOI":"10.1145\/800139.804528"},{"key":"CR8","unstructured":"E. Larsson and Z. Peng, ?Testability Analysis of Behavioral-Level VHDL Secifications?, IEEE European Test Workshop, May 1998."},{"key":"CR9","doi-asserted-by":"crossref","unstructured":"T.-C. Lee, N.K. Jha, and W.H. Wolf, ?Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments?, in Proc. Design Automation Conf., 1993, pp. 292?297.","DOI":"10.1145\/157485.164897"},{"key":"CR10","doi-asserted-by":"crossref","unstructured":"J. Lee and J.H. Patel, ?Testability Analysis Based on Structural and Behavioral Information,? in Proc. of VLSI Test Symp., 1993, pp. 139?146.","DOI":"10.1109\/VTEST.1993.313335"},{"issue":"10","key":"CR11","doi-asserted-by":"crossref","first-page":"1288","DOI":"10.1109\/43.317464","volume":"13","author":"J. Lee","year":"1994","unstructured":"J. Lee and J.H. Patel, ?Architectural Level Test Generation for Microprocessors?, IEEE Trans. CAD, vol. 13, no. 10, pp. 1288?1300, 1994.","journal-title":"IEEE Trans. CAD"},{"issue":"6","key":"CR12","first-page":"61","volume":"C-41","author":"H.-T. Liaw","year":"1992","unstructured":"H.-T. Liaw and C.-S. Lin, ?On the OBDD-Representation of General Boolean Functions?, IEEE Trans. on Computers, vol. C-41, no. 6, pp. 61?664, 1992.","journal-title":"IEEE Trans. on Computers"},{"key":"CR13","unstructured":"W. Mao and R.K. Gulati, ?Improving Gate Level Fault Coverage by RTL Fault Grading?, in Proc. Int. Test Conf., 1996, pp. 150?159."},{"key":"CR14","doi-asserted-by":"crossref","unstructured":"B.T. Murray and J.P. Hayes, ?Hierarchical Test Generation Using Precomputed Tests for Modules?, in Proc. Int. Test Conf., 1988, pp. 221?229.","DOI":"10.1109\/TEST.1988.207806"},{"issue":"6","key":"CR15","doi-asserted-by":"crossref","first-page":"668","DOI":"10.1109\/T-C.1975.224279","volume":"C-24","author":"K.P. Parker","year":"1975","unstructured":"K.P. Parker and E.J. McCluskey, ?Probabilistic Treatment of General Combinational Networks?, IEEE Trans. on Computers, vol. C-24, no. 6, pp. 668?670, 1975.","journal-title":"IEEE Trans. on Computers"},{"key":"CR16","unstructured":"J. Raik and R. Ubar, ?Fast Test Pattern Generation for Sequential CircuitsUsing Decision Diagram Representations?, JETTA, Kluwer Academic Publishers. vol. 16, no. 3, pp. 213?226, 2000."},{"key":"CR17","unstructured":"I.M. Ratiu, ?VICTOR: A Fast VLSI Testability Analysis Program,? in Proc. IEEE International Test Conf., 1982, pp. 397?401."},{"key":"CR18","unstructured":"R. Ubar, ?Test Generation for Digital Circuits Using Alternative Graphs?, in Proc. of Tallinn Technical University, no. 409, pp. 75?81, 1976."},{"key":"CR19","doi-asserted-by":"crossref","unstructured":"R. Ubar, ?Test Synthesis with Alternative Graphs,? IEEE Design & Test of Computers, Spring 1996, pp. 48?57.","DOI":"10.1109\/54.485782"},{"key":"CR20","first-page":"141","volume":"4","author":"R. Ubar","year":"1998","unstructured":"R. Ubar, Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams, OPA (Overseas Publishers Assotiation) N.V. Gordon and Breach Publishers, Multiple Valued Logic, vol. 4, pp. 141?157, 1998.","journal-title":"Multiple Valued Logic"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-5288-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-005-5288-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-5288-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T21:57:39Z","timestamp":1559253459000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-005-5288-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,2]]},"references-count":20,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2005,2]]}},"alternative-id":["5288"],"URL":"https:\/\/doi.org\/10.1007\/s10836-005-5288-5","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2005,2]]}}}