{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:29:21Z","timestamp":1761560961672,"version":"3.32.0"},"reference-count":43,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2005,6,1]],"date-time":"2005-06-01T00:00:00Z","timestamp":1117584000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2005,6]]},"DOI":"10.1007\/s10836-005-6356-6","type":"journal-article","created":{"date-parts":[[2005,4,6]],"date-time":"2005-04-06T14:47:17Z","timestamp":1112798837000},"page":"267-281","source":"Crossref","is-referenced-by-count":1,"title":["Detection and Evaluation of Deterministic Jitter Causes in CP-PLL?s Due to Macro Level Faults and Pre-Detection Using Simple Methods"],"prefix":"10.1007","volume":"21","author":[{"given":"Martin John","family":"Burbidge","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"CR1","unstructured":"Agilent Technologies Advanced Design System (ADS), http:\/\/eesof.tm.agilent.com (active September 2004)"},{"key":"CR2","unstructured":"F. Azais, M. Renovell, Y.Bertrand, A. Ivanov, and S. Tabatabaei, ?A Unified Digital Test Technique For PLL?s; Catastophic Faults Covered,? in Proc. 5th Int. Mixed Signal Testing Workshop."},{"key":"CR3","unstructured":"D. Banerjee, (National Semiconductors) PLL Performance Simulation and Design, Second Edition, 2001, http:\/\/www.national.com\/appinfo\/wireless\/files\/DeansBook_4_01.pdf (active September 2004)"},{"key":"CR4","unstructured":"R.E. Best, Phase-Locked Loops; Design, Simulation and Applications, Fourth edition, McGraw-Hill, 1999, ISBN 0-07-134903?0."},{"key":"CR5","unstructured":"M.J. Burbidge, A. Lechner, and A. Richardson, ?Test Techniques for Embedded Charge-Pump Phase-Locked Loops; Problems, Current BIST Techniques, and Alternative Suggestions,? 7th IEEE International Mixed Signal Test Workshop, June 13th?15th, 2001."},{"key":"CR6","unstructured":"M.J. Burbidge, J. Tijou, and F. Poullet, ?Investigations For Minimum Invasion Digital Only Built In ?Ramp? Based Test Techniques For Charge Pump PLL?s,? Journal of Electronic Testing Theory and Applications (JETTA), vol. 19, no. 4 (Kluwer Academic Publishers)."},{"key":"CR7","unstructured":"M.J. Burbidge, A. Richardson, and A. Lechner, ?Evaluation and Detection of Deterministic Jitter Causes in CP-PLL?s due to Macro Level Faults and Pre-Detection Using Simple Methods,? in 9th IEEE International Mixed Signal Test Workshop, June 2003."},{"key":"CR8","unstructured":"A.H. Chan and G. Roberts, ?A Synthesizable, Fast and High-Resolution Timing Measurement Device Using A component-Invariant Vernier Delay Linevol. 2,? in ITC International Test Conference, 2001."},{"key":"CR9","unstructured":"F.R. Connor, ?Introductory Topics in Electronics and Telecommunication: Modulation?, 2nd edition, Edward Arnold, 1987, ISBN 0-7131-3457-7."},{"key":"CR10","unstructured":"M. Curtin and P. O?brien, ?Phase-Locked Loops for High-Frequency Receivers and Transmitters? Parts 1 to 3, Analogue Devices, Analogue Dialogue, Issues 33-3, 33-5 and 33-7, 1999."},{"key":"CR11","unstructured":"A. DeHon, ?In-System Timing Extraction and Control through Scan-Based, Test-Access Ports,? M.I.T Transit Project, Transit Note #102, 1994"},{"key":"CR12","unstructured":"Fluence VCOBIST Presentation; http:\/\/www.fluence.com\/bistmaxx\/present_vco\/sld003.htm (active February 2004)."},{"key":"CR13","doi-asserted-by":"crossref","first-page":"1849","DOI":"10.1109\/TCOM.1980.1094619","volume":"COM-28","author":"F.M. Gardner","year":"1980","unstructured":"F.M. Gardner, ?Charge-Pump Phase-Locked Loops,? IEEE Communications Transactions, vol. COM-28, pp. 1849?1858, 1980.","journal-title":"IEEE Communications Transactions"},{"key":"CR14","unstructured":"N. Godmabe, C.-J. Rchard Shi, and M. Soma (eds.), ?Behavioural Lvel Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS,? Journal of Electronic Testing Theory and Applications (JETTA), vol. 13, no. 1, 1998. (Kluwer Academic Publishers)."},{"key":"CR15","unstructured":"B.-G. Goldberg, ?Digital Frequency Synthesis Demystified,? pub. LLH Technical Publishing, 1999, ISBN: 01-878707-47?7."},{"key":"CR16","unstructured":"P. Horowitz and W. Hill, The Art of Electronics, 1st edition, Cambridge University Press, pp. 621?623."},{"key":"CR17","doi-asserted-by":"crossref","unstructured":"Introduction to IEEE special issue on Gigabit Wireless, N. Jayant (ed.), vol. 92, no. 9, pp. 195?197, 2004.","DOI":"10.1109\/JPROC.2003.821917"},{"issue":"17","key":"CR18","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1109\/54.844337","volume":"2","author":"K. Jenkins","year":"2000","unstructured":"K. Jenkins and J. Eckhardt, ?Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops,? IEEE Design and Test of Computers, vol. 2, no. 17, pp. 86?93 2000.","journal-title":"IEEE Design and Test of Computers"},{"key":"CR19","unstructured":"D.A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons Inc, 1997, pp. 648?695, ISBN 0-471-14448-7."},{"key":"CR20","doi-asserted-by":"crossref","unstructured":"S. Kim and M. Soma, ?An Effective Defect-Oriented BIST Architecture for High Speed Phase Locked Loops?, in IEEE VLSI Test Symposium, April 2000, pp. 231?236.","DOI":"10.1109\/VTEST.2000.843850"},{"key":"CR21","unstructured":"S. Kim and M. Soma, ?Test Evaluation and Data on Defect-Oriented BIST Architecture for High-Speed PLL,? in Proc. IEEE International Test Conf., Oct. 2001."},{"key":"CR22","doi-asserted-by":"crossref","first-page":"2244","DOI":"10.1109\/TCOM.1982.1095404","volume":"COM-30","author":"V.F. Kroupa","year":"1982","unstructured":"V.F. Kroupa, ?Noise Properties of PLL Systems,? IEE Communications Transactions, vol. COM-30, pp. 2244?2252, 1982.","journal-title":"IEE Communications Transactions"},{"key":"CR23","unstructured":"K. Kundert, ?Modelling and Simulation of Jitter in PLL Frequency Synthesizers,? Cadence White Paper 1998, \u00a9Cadence Design Systems 2001."},{"key":"CR24","doi-asserted-by":"crossref","first-page":"1113","DOI":"10.1109\/4.933469","volume":"36","author":"P. Larson","year":"2001","unstructured":"P. Larson, ?Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise,? IEEE Journal of Solid-State Circuits, vol. 36, pp. 1113?1120, 2001.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"CR25","unstructured":"T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998, pp. 438?549, ISBN 0-521-63922-0."},{"issue":"2","key":"CR26","doi-asserted-by":"crossref","first-page":"179","DOI":"10.1109\/4.658619","volume":"33","author":"A. Hajimiri","year":"1998","unstructured":"A. Hajimiri and T.H. Lee, ?A General Theory of Phase Noise,? IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179?194, 1998.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"CR27","doi-asserted-by":"crossref","unstructured":"M. Li, ?Requirements, Challenges, and Solutions for Testing Multiple GB\/s ICs In Production,? in ITC International Test Conference 2003, Panel 8.3 Keynote, pp. 1309.","DOI":"10.1109\/TEST.2003.1271149"},{"key":"CR28","unstructured":"M. Loewen, ?Basic PLL Filters for the rfPIC? \/rfHCS?, Microchip Technology Inc, Application Note AN846, 2002."},{"key":"CR29","doi-asserted-by":"crossref","unstructured":"G.A.S. Machado, (ed.), Low Power HF Microelectronics a Unified Approach, IEE Circuits and Systems Press, 1996, ISBN 0852968744.","DOI":"10.1049\/PBCS008E"},{"key":"CR30","unstructured":"R. Poore, ?Phase Noise and Jitter,? Agilent Advanced Design System (ADS) Application Note, Agilent Technologies, 2001."},{"key":"CR31","doi-asserted-by":"crossref","unstructured":"E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, ?An Integrated Time-to-Digital Converter with 30-ps Single-Shot Presicion,? IEEE Journal of Solid State Circuits, vol. 35, no. 10, 2000.","DOI":"10.1109\/4.871330"},{"key":"CR32","doi-asserted-by":"crossref","unstructured":"B. Razavi, ?Analysis, Modelling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators,? in Proc CICC, May 1995, pp. 323?326.","DOI":"10.1109\/CICC.1995.518195"},{"key":"CR33","doi-asserted-by":"crossref","unstructured":"B. Razavii, (ed.), Monolithic Phase-locked Loops and Clock Recovery Circuits, IEEE Press, ISBN 0-7803-1149-3.","DOI":"10.1109\/9780470545331"},{"key":"CR34","unstructured":"?Reduced Timing Jitter and Phase Noise in Radio-Frequency PLLs?, Avant Electronics Journal Technical Article, March 1999."},{"key":"CR35","unstructured":"?Separating Jitter Sources; Frequency selective separation of jitter components? Lecroy Application Brief, No Lab 754"},{"key":"CR36","unstructured":"M. Smith, ?An Improved PLL Design Method Without ? n and ? ?, Motorola application note AN1253, 1998."},{"key":"CR37","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1016\/S0167-9260(98)00026-1","volume":"26","author":"M. Soma","year":"1998","unstructured":"M. Soma, ?Mixed-Signal On-Chip Timing Measurements,? Integration, the VLSI journal, vol. 26, pp. 151?165, 1998, (Elsevier).","journal-title":"Integration, the VLSI journal"},{"key":"CR38","doi-asserted-by":"crossref","unstructured":"S. Sunter and A. Roy, ?BIST for Phased Locked Loops in Digital Applications,? in IEEE International Test Conf, 1999, pp. 532?540.","DOI":"10.1109\/TEST.1999.805777"},{"key":"CR39","unstructured":"S. Tabatabaei, and A. Ivanov, ?An Embedded Core for High Accuracy Testing of IC Timing Circuit Specifications,?in 8th IEEE International Mixed Signal Test Workshop, 2002."},{"key":"CR40","unstructured":"Tektronix Application Note, ?Analysing Jitter Using a Spectrum Based Approach?. Application Note No 55-15631."},{"key":"CR41","doi-asserted-by":"crossref","unstructured":"B.R. Veillette and G.W. Roberts, ?Stimulus Generation for Built-in Self-Test of Charge-Pump Phase-Locked Loops,? in Proc. IEEE International Test Conference, Washington D.C., Oct. 1998, pp. 698?707.","DOI":"10.1109\/TEST.1998.743214"},{"issue":"3","key":"CR42","doi-asserted-by":"crossref","first-page":"483","DOI":"10.1109\/4.661214","volume":"33","author":"B.R. Veillette","year":"1998","unstructured":"B.R. Veillette and G.W. Roberts, ?On-Chip Measurement of the Jitter Transfer Function of Charge Pump Phase Locked Loops,? IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 483?491, 1998.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"CR43","doi-asserted-by":"crossref","first-page":"1737","DOI":"10.1109\/PROC.1963.2686","volume":"51","author":"A.J. Viterbi","year":"1963","unstructured":"A.J. Viterbi, ?Phase-Locked Loop Dynamics in the Presence of Noise by Fokker-Planck Techniques,? Proc. IEEE, vol. 51, pp. 1737?1753, 1963.","journal-title":"Proc. IEEE"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-6356-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-005-6356-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-005-6356-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,31]],"date-time":"2024-12-31T01:24:40Z","timestamp":1735608280000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-005-6356-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,6]]},"references-count":43,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2005,6]]}},"alternative-id":["6356"],"URL":"https:\/\/doi.org\/10.1007\/s10836-005-6356-6","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2005,6]]}}}