{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:09:27Z","timestamp":1763467767641},"reference-count":19,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2007,1,24]],"date-time":"2007-01-24T00:00:00Z","timestamp":1169596800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2007,2]]},"DOI":"10.1007\/s10836-006-0403-9","type":"journal-article","created":{"date-parts":[[2007,1,22]],"date-time":"2007-01-22T11:09:07Z","timestamp":1169464147000},"page":"47-54","source":"Crossref","is-referenced-by-count":15,"title":["Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs"],"prefix":"10.1007","volume":"23","author":[{"given":"L.","family":"Sterpone","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Sonza Reorda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Violante","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F. Lima","family":"Kastensmidt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Carro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2007,1,24]]},"reference":[{"key":"10403_CR1","unstructured":"M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Cerchia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, and P. Zambolin, \u201cEvaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-based FPGA,\u201d in IEEE Design Automation and Test in Europe, 2004, pp. 188\u2013193."},{"key":"10403_CR2","doi-asserted-by":"crossref","unstructured":"P. Bernardi, M. Sonza Reorda, L. Sterpone, and M. Violante, \u201cOn the Evaluation of SEUs Sensitiveness in SRAM-based FPGAs,\u201d in 10th IEEE International On-line Testing Symposium, 2004, pp. 115\u2013120.","DOI":"10.1109\/OLT.2004.1319668"},{"key":"10403_CR3","unstructured":"C. Carmichael, \u201cTriple Module Redundancy Design Techniques for Virtex FPGAs,\u201d in Xilinx Application Notes XAPP197, 2001."},{"key":"10403_CR4","unstructured":"\u201cCorrecting Single-Event Upset Through Virtex Partial Reconfiguration,\u201d in Xilinx Application Notes XAPP216, 2000."},{"key":"10403_CR5","unstructured":"E. Fuller, M. Caffrey, P. Blain, C. Carmichael, N. Khalsa, A. Salazar, \u201cRadiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing,\u201d in MAPLD 1999 Proceedings, C_2, September 1999."},{"key":"10403_CR6","doi-asserted-by":"crossref","unstructured":"F. Lima Kanstensmidt, G. Neuberger, R. Hentschke, L. Carro, and R. Reis, \u201cDesigning Fault-Tolerant Techniques for SRAM-based FPGAs,\u201d in IEEE Design & Test of Computers, Nov\u2013Dec 2004, pp. 552\u2013562.","DOI":"10.1109\/MDT.2004.85"},{"key":"10403_CR7","doi-asserted-by":"crossref","first-page":"1290","DOI":"10.1109\/DATE.2005.229","volume":"2","author":"F.L. Kanstensmidt","year":"2005","unstructured":"F.L. Kanstensmidt, L. Sterpone, L. Carro, and M. Sonza Reorda, \u201cOn the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs,\u201d in Design, Automation and Test in Europe, vol. 2, 2005, pp. 1290\u20131295.","journal-title":"Design, Automation and Test in Europe"},{"key":"10403_CR8","doi-asserted-by":"crossref","unstructured":"M. Nikolaidis, \u201cTime Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies,\u201d in IEEE 17th VLSI Test Symposium, April 1999, pp. 86\u201394.","DOI":"10.1109\/VTEST.1999.766651"},{"issue":"6","key":"10403_CR9","doi-asserted-by":"crossref","first-page":"2742","DOI":"10.1109\/23.556861","volume":"43","author":"E. Normand","year":"1996","unstructured":"E. Normand, \u201cSingle Event Upset at Ground Level,\u201d IEEE Transactions on Nuclear Science, vol. 43, no. 6, 2742\u20132750, 1996 (Dec.).","journal-title":"IEEE Transactions on Nuclear Science"},{"key":"10403_CR10","doi-asserted-by":"crossref","unstructured":"M. Ohlsson, P. Dyreklev, K. Johansson, and P. Afke, \u201cNeutron Single Event Upsets in SRAM-based FPGAs,\u201d in Radiation Effects and Data Workshop, 1998, pp. 177\u2013180.","DOI":"10.1109\/REDW.1998.731500"},{"issue":"7","key":"10403_CR11","doi-asserted-by":"crossref","first-page":"1013","DOI":"10.1109\/5.231340","volume":"81","author":"J. Rose","year":"1993","unstructured":"J. Rose, A. El Gamal, and A. Sangiovanni-Vincetelli, \u201cArchitecture of Field-Programmable Gate Arrays,\u201d IEEE Procedings, vol. 81, no. 7, pp. 1013\u20131029, 1993 (July).","journal-title":"IEEE Procedings"},{"key":"10403_CR12","unstructured":"S Habinc Gaisler Research, \u201cFunctional Triple Modular Redundancy (FTMR) VHDL Design Methodology for Redundancy in Combinational and Sequential logic,\u201d www.gaisler.com ."},{"issue":"5","key":"10403_CR13","doi-asserted-by":"crossref","first-page":"2957","DOI":"10.1109\/TNS.2004.834955","volume":"51","author":"P.K. Samudrala","year":"2004","unstructured":"P.K. Samudrala, J. Ramos, and S. Katkoori, \u201cSelective Triple Modular Redundancy (STMR) Based Single-Event Upset (SEU) Tolerant Synthesis for FPGAs,\u201d IEEE Transactions on Nuclear Science, vol. 51, no. 5, pp. 2957\u20132969, 2004 (Oct.).","journal-title":"IEEE Transactions on Nuclear Science"},{"key":"10403_CR14","doi-asserted-by":"crossref","unstructured":"M. Sonza Reorda, L. Sterpone, and M. Violante, \u201cMultiple Errors Provoked by SEUs in the FPGA Configuration Memory: A Possible Solution,\u201d in 10th IEEE European Test Symposium, 2005, pp. 136\u2013141.","DOI":"10.1109\/ETS.2005.29"},{"key":"10403_CR15","unstructured":"\u201cSpartan-II 2.5 V FPGA family: Introduction and Ordering Information,\u201d in Xilinx Product Specification Datasheets, 2003."},{"key":"10403_CR16","doi-asserted-by":"crossref","unstructured":"C. Stroud, J. Nall, M. Lashinsky, and M. Abramovici, \u201cBIST-Based Diagnosis of FPGA Interconnect,\u201d in Proceedings of the IEEE International Test Conference, 2002, pp. 618\u2013627.","DOI":"10.1109\/TEST.2002.1041813"},{"key":"10403_CR17","unstructured":"\u201cTMRTool User Guide,\u201d in Xilinx User Guide UG156, 2004."},{"key":"10403_CR18","unstructured":"\u201cVirtex 2.5 FPGA family: Introduction and Ordering Information,\u201d in Xilinx Product Specification Datasheets, 2001."},{"key":"10403_CR19","doi-asserted-by":"crossref","unstructured":"M. Wirthlin, E. Johnson, N. Rollins, M. Caffrey, and P. Graham, \u201cThe Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets,\u201d in Proc. 11th Ann. IEEE Symposium on Field-Programmable Custom Computing Machines, 2003, pp. 133\u2013142.","DOI":"10.1109\/FPGA.2003.1227249"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-0403-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-006-0403-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-0403-9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,31]],"date-time":"2019-05-31T01:57:40Z","timestamp":1559267860000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-006-0403-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,1,24]]},"references-count":19,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,2]]}},"alternative-id":["10403"],"URL":"https:\/\/doi.org\/10.1007\/s10836-006-0403-9","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,1,24]]}}}