{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,8]],"date-time":"2025-01-08T22:10:18Z","timestamp":1736374218542,"version":"3.32.0"},"reference-count":29,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2006,2,1]],"date-time":"2006-02-01T00:00:00Z","timestamp":1138752000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2006,2]]},"DOI":"10.1007\/s10836-006-4835-z","type":"journal-article","created":{"date-parts":[[2006,5,8]],"date-time":"2006-05-08T17:54:22Z","timestamp":1147110862000},"page":"11-22","source":"Crossref","is-referenced-by-count":1,"title":["Scaling of iDDT Test Methods for Random Logic Circuits"],"prefix":"10.1007","volume":"22","author":[{"given":"Ali","family":"Chehab","sequence":"first","affiliation":[]},{"given":"Saurabh","family":"Patel","sequence":"additional","affiliation":[]},{"given":"Rafic","family":"Makki","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"4835_CR1","doi-asserted-by":"crossref","unstructured":"J. Abraham and R. Tupuri, \u201cA Comprehensive Fault Model for Deep Submicron Digital Circuits,\u201d International Workshop on Electronic Design, Test, and Applications, 2002, pp. 360\u2013364.","DOI":"10.1109\/DELTA.2002.994650"},{"key":"4835_CR2","doi-asserted-by":"crossref","unstructured":"Bapiraju Vinnakota, Wanli Jiang, and D. Sun, \u201cProcess-Tolerant Test with Energy Consumption Ratio,\u201d International Test Conference, 1998,Vol. pp. 1027\u20131036.","DOI":"10.1109\/TEST.1998.743300"},{"key":"4835_CR3","unstructured":"D. Binkley, R. Makki, T. Weldon, and A. Chehab, \u201cMethod and Apparatus for Testing Electronic Circuits,\u201d US Utility Patent Application, serial number 10\/237, 670."},{"key":"4835_CR4","unstructured":"A. Chehab, R. Makki, M. Spica, and D. Wu, \u201cAnalysis of iDDT for Defect Detection and Classification in Very Deep Sub-micron CMOS Circuits,\u201d Sixth World Multi-conference on Systemics, Cybernetics, and Informatics, 2002."},{"key":"4835_CR5","unstructured":"K.T. Cheng, \u201cTransition Fault Testing for Sequential Circuits,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993."},{"key":"4835_CR6","doi-asserted-by":"crossref","unstructured":"A. Germida, Z. Yan, J. Plusquellic, and F. Muradali, \u201cDefect Detection using Power Supply Transient Signal Analysis,\u201d International Test Conference, 1999,Vol. pp. 67\u201376.","DOI":"10.1109\/TEST.1999.805615"},{"key":"4835_CR7","doi-asserted-by":"crossref","unstructured":"W. Jiang and B. Vinnakota, \u201cStatistical Threshold Formulation for Dynamic Test,\u201d International Test Conference, 1999,Vol. pp. 57\u201366.","DOI":"10.1109\/TEST.1999.805614"},{"key":"4835_CR8","doi-asserted-by":"crossref","unstructured":"B. Kruseman, P. Janssen, and V. Zieren, \u201cTransient Current Testing of 0.25\u00a0\u03bcm CMOS Devices,\u201d International Test Conference, 1999,Vol. pp. 47\u201356.","DOI":"10.1109\/TEST.1999.805613"},{"key":"4835_CR9","unstructured":"Y. Levendel and P.R. Menon, \u201cTransition Faults in Combinational Circuits: Input Transition test Generation and Fault Simulation,\u201d International Fault Tolerant Computing Symposium, 1986,Vol. pp. 278\u2013283."},{"key":"4835_CR10","unstructured":"W.N. Li, S.M. Reddy, and S.K. Sahni, \u201cOn Path Selection in Combinational Logic Circuits,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1989."},{"key":"4835_CR11","unstructured":"J. Liu, R. Makki, A. Kayssi, and S. Su, \u201cAn Economical Method for Detecting Disturb Faults in CMOS SRAMs,\u201d IEEE Proceedings of the Economics of Design, Test and Manufacture,1996."},{"key":"4835_CR12","doi-asserted-by":"crossref","unstructured":"A.K. Majhi, J. Jacob, L.M. Patnaik, and V.D. Agrawal, \u201cOn Test Coverage of Path Delay Faults,\u201d 9th International Conference on VLSI Design, 1996,Vol. pp. 418\u2013421.","DOI":"10.1109\/ICVD.1996.489645"},{"key":"4835_CR13","doi-asserted-by":"crossref","unstructured":"R. Makki, S. Su, and T. Nagle, \u201cTransient Power Supply Current Testing of Digital CMOS Circuits,\u201d International Test Conference, 1995,Vol. pp. 892\u2013901.","DOI":"10.1109\/TEST.1995.529922"},{"key":"4835_CR14","doi-asserted-by":"crossref","unstructured":"Y.K. Malaiya and R. Narayanaswamy, \u201cModeling and Testing for Timing Defects in Synchronous Sequential Circuits,\u201d Design and Test of Computers, 1984.","DOI":"10.1109\/MDT.1984.5005692"},{"key":"4835_CR15","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1023\/A:1008337200506","volume":"13","author":"Y. Min","year":"1998","unstructured":"Y. Min and Z. Li, \u201cIDDT Testing versus IDDQ Testing,\u201d Journal of Electronic Testing, Theory and Applications, Vol. 13,Vol. pp. 51\u201355, 1998.","journal-title":"Journal of Electronic Testing, Theory and Applications"},{"key":"4835_CR16","doi-asserted-by":"crossref","unstructured":"A. Mukherjee, K. Wang, L.-H. Chen, and M. Marek-Sadowska, \u201cSizing Power\/Ground Meshes for Clocking and Computing Circuit Components,\u201d Design Automation and Test in Europe, 2002,Vol. pp.176\u2013183.","DOI":"10.1109\/DATE.2002.998267"},{"key":"4835_CR17","doi-asserted-by":"crossref","unstructured":"W. Needham, C. Prunty, and E. Yeoh, \u201cHigh Volume Test Escapes, An Analysis of Defects our Tests are Missing,\u201d International Test Conference, 1998,Vol. pp. 25\u201334.","DOI":"10.1109\/TEST.1998.743133"},{"key":"4835_CR18","doi-asserted-by":"crossref","unstructured":"J.F. Plusquellic, D.M. Chiarulli, and S.P. Levitan, \u201cDigital Integrated Circuit Testing using Transient Signal Analysis,\u201d International Test Conference, 1996,Vol. pp. 481\u2013490.","DOI":"10.1109\/TEST.1996.557062"},{"key":"4835_CR19","doi-asserted-by":"crossref","unstructured":"J. Plusquellic, D. Chiarulli, and S. Levitan, \u201cCharacterization of CMOS Defects using Transient Signal Analysis,\u201d DFT, 1998,Vol. pp. 93\u2013101.","DOI":"10.1109\/DFTVS.1998.732155"},{"key":"4835_CR20","doi-asserted-by":"crossref","unstructured":"J.F. Plusquellic, D.M. Chiarulli, and S.P. Levitan, \u201cIdentification of Defective CMOS Devices using Correlation and Regression Analysis of Frequency Domain Transient Signal Data,\u201d International Test Conference, 1997,Vol. pp. 40\u201349.","DOI":"10.1109\/TEST.1997.639592"},{"key":"4835_CR21","doi-asserted-by":"crossref","unstructured":"M. Sachdev, P. Janssen, and V. Zieren, \u201cDefect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS ICs,\u201d International Test Conference, 1998,Vol. pp.204\u2013213.","DOI":"10.1109\/TEST.1998.743153"},{"key":"4835_CR22","doi-asserted-by":"crossref","unstructured":"M.H. Schulz and F. Brglez, \u201cAccelerated Transition Fault Simulation\u201d, 26th Design Automation Conference, 1987,Vol. pp. 237\u2013243.","DOI":"10.1145\/37888.37923"},{"issue":"6","key":"4835_CR23","doi-asserted-by":"crossref","first-page":"441","DOI":"10.1049\/el:19990359","volume":"35","author":"J. Seguera","year":"1999","unstructured":"J. Seguera, I. de Paul, M. Roca, E. Isern, and C. Hawkins, \u201cExperimental Analysis of Transient Current Testing Based on Charge Observation\u201d, Electronic Letters, Vol. 35, No. 6, 1999,Vol. pp. 441\u2013443.","journal-title":"Electronic Letters"},{"key":"4835_CR24","doi-asserted-by":"crossref","unstructured":"S. Su, R. Makki, and T. Nagle, \u201cTransient Power Supply Current Monitoring\u2014A New Test Method for CMOS VLSI Circuits,\u201d Journal of Electronic Testing: Theory and Applications,Vol. pp. 23\u201343, 1995.","DOI":"10.1007\/BF00993128"},{"key":"4835_CR25","doi-asserted-by":"crossref","unstructured":"B. Vinnakota, \u201cMonitoring Power Dissipation for Fault Detection,\u201d 14th VLSI Test Symposium, 1996,Vol. pp. 483\u2013488.","DOI":"10.1109\/VTEST.1996.510897"},{"key":"4835_CR26","doi-asserted-by":"crossref","unstructured":"J.A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, \u201cTransition Fault Simulation,\u201d IEEE Design and Test of Computers, 1987.","DOI":"10.1109\/MDT.1987.295104"},{"key":"4835_CR27","doi-asserted-by":"crossref","unstructured":"Wanli Jiang, and Bapiraju Vinnakota, \u201cIC Test Using the Energy Consumption Ratio,\u201d IEEE Design Automation Conference, 1999,Vol. pp. 976\u2013981.","DOI":"10.1145\/309847.310109"},{"key":"4835_CR28","unstructured":"Masahiro Ishida, Dong Sam Ha, Takahiro Yamaguchi, Yoshihiro Hashimoto, and Tadahiro Ohmi, \u201cIDDT Testing: An Efficient Method for Detecting Delay Faults and Open Defects,\u201d IEEE International Workshop on Defect Based Testing, Los Angeles, 2001."},{"key":"4835_CR29","doi-asserted-by":"crossref","unstructured":"A. Chehab, A. Kayssi, A. Nazer, and R. Makki, \u201cAn Improved Method for iDDT Testing in the Presence of Leakage and Process Variation,\u201d in Proc. IEEE International Workshop on Defect Based Testing, Napa, California, 2004,Vol. pp. 11\u201316.","DOI":"10.1109\/DBT.2004.1408946"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-4835-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-006-4835-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-4835-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,8]],"date-time":"2025-01-08T21:49:03Z","timestamp":1736372943000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-006-4835-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,2]]},"references-count":29,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2006,2]]}},"alternative-id":["4835"],"URL":"https:\/\/doi.org\/10.1007\/s10836-006-4835-z","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2006,2]]}}}