{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T04:58:43Z","timestamp":1757307523643},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2006,4,1]],"date-time":"2006-04-01T00:00:00Z","timestamp":1143849600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2006,4]]},"DOI":"10.1007\/s10836-006-6674-3","type":"journal-article","created":{"date-parts":[[2006,5,15]],"date-time":"2006-05-15T06:49:00Z","timestamp":1147675740000},"page":"125-142","source":"Crossref","is-referenced-by-count":13,"title":["Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability"],"prefix":"10.1007","volume":"22","author":[{"given":"Hafizur","family":"Rahaman","sequence":"first","affiliation":[]},{"given":"Debesh K.","family":"Das","sequence":"additional","affiliation":[]},{"given":"Bhargab B.","family":"Bhattacharya","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"5","key":"6674_CR1","first-page":"710","volume":"12","author":"D.L. Dietmeyer","year":"1993","unstructured":"D.L. Dietmeyer, \u201cGenerating Minimal Covers of Symmetric Function,\u201d IEEE TCAD, Vol. 12, No. 5, pp. 710\u2013713, 1993.","journal-title":"IEEE TCAD"},{"key":"6674_CR2","first-page":"772","volume":"14","author":"W. Ke","year":"1995","unstructured":"W. Ke and P.R. Menon, \u201cDelay-Testable Implementations of Symmetric Functions,\u201d IEEE TCAD, Vol. 14, pp. 772\u2013775, 1995.","journal-title":"IEEE TCAD"},{"key":"6674_CR3","first-page":"1076","volume":"19","author":"S. Chakraborty","year":"September 2000","unstructured":"S. Chakraborty, S. Das, D.K. Das, and B.B. Bhattacharya, \u201cSynthesis of Symmetric Functions for Path-Delay Fault Testability,\u201d IEEE TCAD, Vol. 19, pp. 1076\u20131081, September 2000.","journal-title":"IEEE TCAD"},{"key":"6674_CR4","volume-title":"Switching and Finite Automata Theory","author":"Z. Kohavi","year":"1977","unstructured":"Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1977."},{"issue":"3","key":"6674_CR5","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1007\/BF00202268","volume":"8","author":"Y.X. Yang","year":"1995","unstructured":"Y.X. Yang and B. Guo, \u201cFurther enumerating boolean functions of cryptographic significance,\u201d J. Cryptology, Vol. 8, No. 3, pp. 115\u2013122, 1995.","journal-title":"J. Cryptology"},{"issue":"11","key":"6674_CR6","first-page":"1301","volume":"120","author":"S.L. Hurst","year":"1973","unstructured":"S.L. Hurst, \u201cDigital Summation Threshold Logic Gates: A New Circuit Element,\u201d IEE Proc., Vol. 120, No. 11, pp. 1301\u20131307, 1973.","journal-title":"IEE Proc."},{"key":"6674_CR7","unstructured":"J. Ja\u2032 Ja\u2032 and S.M. Wu, \u201cA New Approach to Realize Partially Symmetric Functions,\u201d Tech. Rep. SRC TR 86\u201354, Dept. EE, University of Maryland, 1986."},{"key":"6674_CR8","unstructured":"H. Rahaman, D.K. Das, and B.B. Bhattacharya, \u201cA Simple Delay-Testable Design of Digital Summation Threshold Logic (DSTL) Array,\u201d in Proc. 5th International Workshop on Boolean Problems, Freiberg, Germany, September 2002."},{"key":"6674_CR9","doi-asserted-by":"crossref","unstructured":"H. Rahaman, D.K. Das, and B.B. Bhattacharya, \u201cA New Synthesis of Symmetric Functions,\u201d in Proc. Int. Conf. ASP-DAC\/VLSI Design, 2002, pp. 160\u2013165.","DOI":"10.1109\/ASPDAC.2002.994910"},{"key":"6674_CR10","unstructured":"E.M. Sentovich, et al., \u201cSIS: A Sequential System for Sequential Circuit Synthesis,\u201d Technical Report UCB\/ERL m92\/41. Electronic Research Laboratory, University of California, Berkeley, May 1992."},{"key":"6674_CR11","unstructured":"M. Perkowski, P. Kerntopf, A.Buller, M.C.-Jeske, A. Mishchenko, X. Song, A. Al-Rabadi, L.Jozwiak, A. Coppola, and B. Massey, \u201cRegularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits,\u201d Manuscript, 2001."},{"key":"6674_CR12","doi-asserted-by":"crossref","first-page":"437","DOI":"10.1016\/0026-2692(94)90068-X","volume":"25","author":"P. Picton","year":"1994","unstructured":"P. Picton, \u201cModified Fredkin Gates in Logic Design,\u201d Microelectronics Journal, Vol. 25, pp. 437\u2013441, 1994.","journal-title":"Microelectronics Journal"},{"key":"6674_CR13","unstructured":"G.L. Smith, \u201cModel for Delay Faults Based Upon Paths,\u201d in Proc. Int. Test Conf., 1985, pp. 342\u2013 349."},{"key":"6674_CR14","doi-asserted-by":"crossref","first-page":"694","DOI":"10.1109\/TCAD.1987.1270315","volume":"CAD-6","author":"C.J. Lin","year":"Sept. 1987","unstructured":"C.J. Lin and S.M. Reddy, \u201cOn Delay Fault Testing in Logic Circuits,\u201d IEEE Trans. CAD, Vol. CAD-6, pp. 694\u2013703, Sept. 1987.","journal-title":"IEEE Trans. CAD"},{"key":"6674_CR15","doi-asserted-by":"crossref","first-page":"1264","DOI":"10.1109\/T-C.1971.223126","volume":"C-20","author":"R. Betancourt","year":"1971","unstructured":"R. Betancourt, \u201cDerivation of Minimum Test Sets for Unate Logic circuits,\u201d IEEE Trans. Comput., Vol. C-20, pp. 1264\u20131269, 1971.","journal-title":"IEEE Trans. Comput."},{"key":"6674_CR16","doi-asserted-by":"crossref","first-page":"835","DOI":"10.1109\/TC.1973.5009174","volume":"C-22","author":"S. B. Akers","year":"1973","unstructured":"S. B. Akers, \u201cUniversal Test Sets for Logic Networks,\u201d IEEE Trans. Comput., Vol. C-22, pp. 835\u2013839, 1973.","journal-title":"IEEE Trans. Comput."},{"key":"6674_CR17","doi-asserted-by":"crossref","first-page":"1016","DOI":"10.1109\/T-C.1973.223638","volume":"C-22","author":"S.M. Reddy","year":"Nov. 1973","unstructured":"S.M. Reddy, \u201cComplete Test Set for Logic Functions,\u201d IEEE Trans. Comput., Vol. C-22, pp. 1016\u20131020, Nov. 1973.","journal-title":"IEEE Trans. Comput."},{"key":"6674_CR18","unstructured":"U. Sparmann, et al., \u201cMinimal Delay Test for Unate Gate Networks,\u201d in Proc. Asian Test Symp., pp. 10\u201316, 1997."},{"key":"6674_CR19","doi-asserted-by":"crossref","first-page":"290","DOI":"10.1109\/43.908472","volume":"20","author":"H. Kim","year":"Feb. 2001","unstructured":"H. Kim and J.P. Hayes, \u201cRealization-Independent ATPG for Designs with Unimplemented Blocks,\u201d IEEE Trans. CAD, Vol. 20, pp. 290\u2013306, Feb. 2001.","journal-title":"IEEE Trans. CAD"},{"key":"6674_CR20","unstructured":"S. Yang, \u201cLogic Synthesis and Optimization Benchmarks Guide,\u201d Technical Report 1991-IWLS-UG-Saeyang, Microelectronics Center of North Carolina."}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-6674-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-006-6674-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-6674-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,14]],"date-time":"2020-04-14T21:36:04Z","timestamp":1586900164000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-006-6674-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,4]]},"references-count":20,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2006,4]]}},"alternative-id":["6674"],"URL":"https:\/\/doi.org\/10.1007\/s10836-006-6674-3","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2006,4]]}}}