{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T20:47:00Z","timestamp":1761943620547,"version":"build-2065373602"},"reference-count":15,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2006,6,1]],"date-time":"2006-06-01T00:00:00Z","timestamp":1149120000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2006,6]]},"DOI":"10.1007\/s10836-006-9319-7","type":"journal-article","created":{"date-parts":[[2006,7,27]],"date-time":"2006-07-27T15:12:53Z","timestamp":1154013173000},"page":"239-253","source":"Crossref","is-referenced-by-count":29,"title":["An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults"],"prefix":"10.1007","volume":"22","author":[{"given":"Jack","family":"Smith","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tian","family":"Xia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Charles","family":"Stroud","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2006,7,27]]},"reference":[{"key":"9319_CR1","doi-asserted-by":"crossref","unstructured":"M. Abramovici and C. Stroud, \u201cBIST-Based Delay-Fault Testing in FPGAs,\u201d Proc. Int\u2019l On-Line Testing Workshop, 2002, pp. 131\u2013134.","DOI":"10.1109\/OLT.2002.1030195"},{"issue":"5","key":"9319_CR2","doi-asserted-by":"crossref","first-page":"549","DOI":"10.1023\/A:1025126030727","volume":"19","author":"M. Abramovici","year":"2003","unstructured":"M. Abramovici and C. Stroud, \u201cBIST-Based Delay Fault Testing in Field Programmable Gate Arrays,\u201d J. Electronic Testing: Theory & Applications, vol. 19, no. 5, pp. 549\u2013558, 2003.","journal-title":"J. Electronic Testing: Theory & Applications"},{"key":"9319_CR3","first-page":"1239","volume":"1","author":"E. Chmelar","year":"2003","unstructured":"E. Chmelar, \u201cFPGA Interconnect Delay Fault Testing,\u201d Proc. Int\u2019l Test Conf., 2003, pp. 1239\u20131247.","journal-title":"Proc. IEEE Int\u2019l Test Conf."},{"key":"9319_CR4","unstructured":"http:\/\/www.xilinx.com"},{"key":"9319_CR5","doi-asserted-by":"crossref","unstructured":"J. Liu and S. Simmons, \u201cBIST-Diagnosis of Interconnect Fault Locations in FPGAs,\u201d Proc. Canadian Conf. on Electrical and Computer Engineering, 2003, pp. 207\u2013210.","DOI":"10.1109\/CCECE.2003.1226379"},{"key":"9319_CR6","doi-asserted-by":"crossref","unstructured":"S. McCracken and Z. Zilic, \u201cFPGA Test Time Reduction Through a Novel Interconnect Testing Scheme,\u201d Proc. ACM Int\u2019l Symp. on Field Programmable Gate Arrays, 2002, pp. 136\u2013144.","DOI":"10.1145\/503048.503069"},{"key":"9319_CR7","doi-asserted-by":"crossref","unstructured":"M. Renovell, J. Figueras, and Y. Zorian, \u201cTest of RAM-Based FPGAs: Methodology and Application to Interconnect,\u201d Proc. IEEE VLSI Test Symp., 1997, pp. 230\u2013237.","DOI":"10.1109\/VTEST.1997.600278"},{"issue":"1","key":"9319_CR8","doi-asserted-by":"crossref","first-page":"45","DOI":"10.1109\/54.655182","volume":"15","author":"M. Renovell","year":"1998","unstructured":"M. Renovell, J. Portal, J. Figueras, and Y. Zorian, \u201cTesting the Interconnect of RAM-Based FPGAs,\u201d IEEE Design & Test of Computers, vol. 15, no. 1, pp. 45\u201350, 1998.","journal-title":"IEEE Design & Test of Computers"},{"key":"9319_CR9","volume-title":"A Designer\u2019s Guide to Built-In Self-Test","author":"C. Stroud","year":"2002","unstructured":"C. Stroud, A Designer\u2019s Guide to Built-In Self-Test, Boston: Kluwer, 2002."},{"key":"9319_CR10","doi-asserted-by":"crossref","unstructured":"C. Stroud, S. Wijesuriya, C. Hamilton, and M. Abramovici, \u201cBuilt-In Self-Test of FPGA Interconnect,\u201d Proc. IEEE Int\u2019l Test Conf., 1998, pp. 404\u2013411.","DOI":"10.1109\/TEST.1998.743180"},{"key":"9319_CR11","doi-asserted-by":"crossref","unstructured":"C. Stroud, K. Leach, and T. Slaughter, \u201cBIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study,\u201d Proc. IEEE Int\u2019l Test Conf., 2003, pp. 1258\u20131268.","DOI":"10.1109\/TEST.2003.1271115"},{"key":"9319_CR12","unstructured":"X. Sun, J. Xu, B. Chan, and P. Trouborst, \u201cnovel Technique for Built-In Self-Test of FPGA Interconnects,\u201d Proc. IEEE Int\u2019l Test Conf., 2000, pp. 795\u2013803."},{"key":"9319_CR13","doi-asserted-by":"crossref","unstructured":"M. Tahoori, \u201cTesting for Resistive Open Defects in FPGAs,\u201d Proc. IEEE Int\u2019l Conf. on Field-Programmable Technology, 2002, pp. 332\u2013335.","DOI":"10.1109\/FPT.2002.1188704"},{"issue":"2","key":"9319_CR14","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1109\/TCAD.2003.822112","volume":"23","author":"M. Tahoori","year":"2004","unstructured":"M. Tahoori and S. Mitra, \u201cTechniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations,\u201d IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, pp. 261\u2013272, 2004.","journal-title":"IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"9319_CR15","unstructured":"S.-J. Wang and C.-N. Huang, \u201cTesting and Diagnosis of Interconnect Structures in FPGAs,\u201d Proc. IEEE Asian Test Symp., 1998, pp. 283\u2013287."}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-9319-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-006-9319-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-9319-7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T03:37:22Z","timestamp":1736480242000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-006-9319-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,6]]},"references-count":15,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2006,6]]}},"alternative-id":["9319"],"URL":"https:\/\/doi.org\/10.1007\/s10836-006-9319-7","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2006,6]]}}}