{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:54:31Z","timestamp":1761580471075,"version":"3.33.0"},"reference-count":19,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2007,2,1]],"date-time":"2007-02-01T00:00:00Z","timestamp":1170288000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2007,2]]},"DOI":"10.1007\/s10836-006-9442-5","type":"journal-article","created":{"date-parts":[[2007,2,2]],"date-time":"2007-02-02T17:54:22Z","timestamp":1170438862000},"page":"11-24","source":"Crossref","is-referenced-by-count":6,"title":["Improve the Quality of Per-Test Fault Diagnosis Using Output Information"],"prefix":"10.1007","volume":"23","author":[{"given":"Chunsheng","family":"Liu","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2007,2,2]]},"reference":[{"key":"9442_CR1","doi-asserted-by":"crossref","unstructured":"B. Arslan and A. Orailoglu, \u201cFault Dictionary Size Reduction Through Test Response Superposition,\u201d Proc. International Conference on Computer Design, pp. 480\u2013485, 2002.","DOI":"10.1109\/ICCD.2002.1106817"},{"key":"9442_CR2","doi-asserted-by":"crossref","unstructured":"T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, \u201cDiagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm,\u201d Proc. International Test Conference, pp. 287\u2013296, 2001.","DOI":"10.1109\/TEST.2001.966644"},{"key":"9442_CR3","doi-asserted-by":"crossref","unstructured":"I. Bayraktaroglu and A. Orailoglu, \u201cGate Level Fault Diagnosis in Scan-Based BIST,\u201d Proc. Design, Automation and Test in Europe, pp. 376\u2013381, 2002.","DOI":"10.1109\/DATE.2002.998301"},{"key":"9442_CR4","doi-asserted-by":"crossref","unstructured":"R. Blanton et al, \u201cFault Tuples in Diagnosis of Deep-Submicron Circuits,\u201d Proc. International Test Conference, pp. 233\u2013241, 2002.","DOI":"10.1109\/TEST.2002.1041765"},{"key":"9442_CR5","doi-asserted-by":"crossref","unstructured":"S. Chakravarty and V. Gopal, \u201cTechniques to Encode and Compress Fault Dictionaries,\u201d Proc. VLSI Test Symposium, pp. 195\u2013200, 1999.","DOI":"10.1109\/VTEST.1999.766665"},{"key":"9442_CR6","doi-asserted-by":"crossref","unstructured":"V. Chickermane, J. Lee, and J. H. Patel, \u201cA Comparative Study of Design for Testability Methods Using High-Level And Gate-Level Descriptions,\u201d Proc. International Conference on Computer-Aided Design, pp. 620\u2013624, 1992.","DOI":"10.1109\/ICCAD.1992.279302"},{"key":"9442_CR7","doi-asserted-by":"crossref","unstructured":"K.N. Dwarakanath and R.D. Blanton, \u201cUniversal Fault Simulation Using Fault Tuples,\u201d Proc. Design Automation Conference, pp. 786\u2013789, 2000.","DOI":"10.1145\/337292.337779"},{"key":"9442_CR8","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9780511816321","volume-title":"Testing of Digital Systems","author":"N. Jha","year":"2003","unstructured":"N. Jha and S. Gupta, Testing of Digital Systems, Cambridge: Cambridge University Press, 2003."},{"key":"9442_CR9","doi-asserted-by":"crossref","unstructured":"D. Lavo and T. Larrabee, \u201cMaking Cause-Effect Effective: Low-Resolution Fault Dictionaries,\u201d Proc. International Test Conference, pp. 278\u2013286, 2001.","DOI":"10.1109\/TEST.2001.966643"},{"key":"9442_CR10","doi-asserted-by":"crossref","unstructured":"D. Lavo, I. Hartanto and T. Larrabee, \u201cMultiplets, Models, and The Search for Meaning: Improving Per-Test Fault Diagnosis,\u201d Proc. International Test Conference, pp. 250\u2013259, 2002.","DOI":"10.1109\/TEST.2002.1041767"},{"key":"9442_CR11","doi-asserted-by":"crossref","unstructured":"I. Pomeranz, S. Venkataraman, S.M. Reddy, and B. Seshadri, \u201cZ-Sets and Z-Detections: Circuit Characteristics That Simplify Fault Diagnosis,\u201d Proc. Design, Automation and Test Europe, pp. 68\u201373, 2004.","DOI":"10.1109\/DATE.2004.1268829"},{"key":"9442_CR12","doi-asserted-by":"crossref","DOI":"10.1515\/9780691214696","volume-title":"A Mathematical Theory of Evidence","author":"G. Shafer","year":"1976","unstructured":"G. Shafer, A Mathematical Theory of Evidence, Princeton, NJ: Princeton University Press, 1976."},{"key":"9442_CR13","doi-asserted-by":"crossref","unstructured":"K. Shigeta and T. Ishiyama, \u201cAn Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction,\u201d Proc. International Test Conference, pp. 235\u2013244, 2000.","DOI":"10.1109\/TEST.2000.894211"},{"key":"9442_CR14","unstructured":"P. Song, F. Motika, D.R. Knebel, R.F. Rizzolo and M.P. Kusko, \u201cS\/390 G5 CMOS Microprocessor Diagnostics,\u201d Proc. International Test Conference, pp. 1073\u20131082, 1999."},{"key":"9442_CR15","doi-asserted-by":"crossref","unstructured":"S. Venkataraman and S. Drummonds, \u201cPOIROT: A Logic Fault Diagnosis Tool and Its Applications,\u201d Proc. International Test Conference, pp. 253\u2013262, 2000.","DOI":"10.1109\/TEST.2000.894213"},{"key":"9442_CR16","doi-asserted-by":"crossref","unstructured":"J. Waicukauski and E. Lindbloom, \u201cFailure Diagnosis of Structured VLSI,\u201d IEEE Design and Test of Computer, pp. 49\u201360, 1989.","DOI":"10.1109\/54.32421"},{"key":"9442_CR17","unstructured":"Z. Wang, K. Tsai, M. Marek-Sadowska, and J. Rajski, \u201cAn Efficient and Effective Methodology on the Multiple Fault Diagnosis,\u201d Proc. International Test Conference, pp. 329\u2013338, 2003."},{"key":"9442_CR18","unstructured":"X. Wen et al, \u201cOn Per-Test Fault Diagnosis Using the X-Fault Model,\u201d Proc. International Conference on Computer Aided Design, pp. 633\u2013640, 2004."},{"key":"9442_CR19","doi-asserted-by":"crossref","unstructured":"P. Wohl, J. Waicukauski, S. Patel, and M. Amin, \u201cEfficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture,\u201d Proc. Design Automation Conference, pp. 566\u2013569, 2003.","DOI":"10.1145\/775832.775976"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-9442-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-006-9442-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-006-9442-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,13]],"date-time":"2025-01-13T07:23:11Z","timestamp":1736752991000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-006-9442-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,2]]},"references-count":19,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,2]]}},"alternative-id":["9442"],"URL":"https:\/\/doi.org\/10.1007\/s10836-006-9442-5","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2007,2]]}}}