{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T00:37:22Z","timestamp":1649032642168},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"1-3","license":[{"start":{"date-parts":[[2008,1,4]],"date-time":"2008-01-04T00:00:00Z","timestamp":1199404800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1007\/s10836-007-5001-y","type":"journal-article","created":{"date-parts":[[2008,1,3]],"date-time":"2008-01-03T16:09:51Z","timestamp":1199376591000},"page":"129-141","source":"Crossref","is-referenced-by-count":0,"title":["Performance-Optimized Design for Parametric Reliability"],"prefix":"10.1007","volume":"24","author":[{"given":"Ramyanshu","family":"Datta","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdulkadir","family":"Utku Diril","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abhijit","family":"Chatterjee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin J.","family":"Nowka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2008,1,4]]},"reference":[{"key":"5001_CR1","unstructured":"Aitken R (2004) Redundancy\u2014it\u2019s not just for defects anymore. In: International workshop on memory technology design and testing. IEEE, 117\u2013120 August 2004"},{"key":"5001_CR2","doi-asserted-by":"crossref","unstructured":"Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V (2003) Parameter variations and impact on circuits and microarchitecture. In: Design automation conference, IEEE, 338\u2013342 June 2003","DOI":"10.1145\/775832.775920"},{"issue":"2","key":"5001_CR3","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1109\/MM.2005.40","volume":"25","author":"P Bose","year":"2005","unstructured":"Bose P (2005) Variation-tolerant design. IEEE Micro 25(2):5\u20135","journal-title":"IEEE Micro"},{"issue":"2","key":"5001_CR4","doi-asserted-by":"crossref","first-page":"183","DOI":"10.1109\/4.982424","volume":"37","author":"KA Bowman","year":"2002","unstructured":"Bowman KA, Duvall SG, Meindl JD (2002) Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J Solid-State Circuits 37(2):183\u2013190","journal-title":"IEEE J Solid-State Circuits"},{"key":"5001_CR5","unstructured":"Cao Y, Sato T, Orshansky M, Sylvester D, Hu C (2000) New paradigm of predictive MOSFET and interconnect modelling for early circuit simulation. In: Custom integrated circuits conference, IEEE, 201\u2013204 June 2000"},{"issue":"4","key":"5001_CR6","doi-asserted-by":"crossref","first-page":"792","DOI":"10.1109\/JSSC.2006.870912","volume":"41","author":"S Das","year":"2006","unstructured":"Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Flautner K, Mudge T (2006) A self-tuning DVS processor using delay-error detection and correction. IEEE J Solid-State Circuits 41(4):792\u2013804","journal-title":"IEEE J Solid-State Circuits"},{"key":"5001_CR7","doi-asserted-by":"crossref","unstructured":"Datta R, Carpenter G, Nowka K, Abraham JA (2006) A scheme for on-chip timing characterization. In: VLSI test symposium, IEEE, 24\u201329 May 2006","DOI":"10.1109\/VTS.2006.11"},{"key":"5001_CR8","doi-asserted-by":"crossref","unstructured":"Datta R, Sebastine A, Raghunathan A, Abraham JA (2004) On-chip delay measurement for silicon debug. In: Great Lakes Symposium on VLSI, ACM, 145\u2013148 April 2004","DOI":"10.1145\/988952.988988"},{"key":"5001_CR9","doi-asserted-by":"crossref","unstructured":"Declerck G (2005) A look into the future of nanoelectronics. In: Symposium on VLSI circuits, IEEE, 6\u201310 June 2005","DOI":"10.1109\/.2005.1469191"},{"key":"5001_CR10","doi-asserted-by":"crossref","unstructured":"Dhar S, Maksimovic D (2001) Switching regulator with dynamically adjustable supply voltage for low power VLSI. In: Annual conference of the IEEE industrial electronics society, IEEE, 1874\u20131879 November\u2013December 2001","DOI":"10.1109\/IECON.2001.975576"},{"key":"5001_CR11","unstructured":"Dhar S, Maksimovic D, Kranzen B (2002) Closed-loop adaptive voltage scaling controller for standard-cell ASICs. In: International symposium on low power electronic design, IEEE, 103\u2013107 August 2002"},{"issue":"2","key":"5001_CR12","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1109\/4.823449","volume":"35","author":"P Dudek","year":"2000","unstructured":"Dudek P, Szczepanski S, Hatfield JV (2000) A high-resolution CMOS time-to-digital converter utilizing a vernier delay line. IEEE Trans Solid-State Circuits 35(2):240\u2013247","journal-title":"IEEE Trans Solid-State Circuits"},{"key":"5001_CR13","unstructured":"Duvall SG (2000) Statistical circuit modeling and optmization. In: International workshop on statistical metrology, IEEE, 56\u201363 June 2000"},{"key":"5001_CR14","doi-asserted-by":"crossref","unstructured":"Genat J-F (1992) High resolution time-to-digital converter. Nucl Instrum Methods A-315:411\u2013414","DOI":"10.1016\/0168-9002(92)90737-O"},{"key":"5001_CR15","doi-asserted-by":"crossref","unstructured":"Kim CH, Roy K, Hsu S, Alvandpour A, Krishnamurthy RK, Borkar S (2003) A process variation compensating technique for sub-90\u00a0nm dynamic circuits. In: Symposium on VLSI circuits, IEEE, 205\u2013206 June 2003","DOI":"10.1109\/VLSIC.2003.1221203"},{"issue":"9","key":"5001_CR16","doi-asserted-by":"crossref","first-page":"523","DOI":"10.1109\/LED.2002.802657","volume":"23","author":"C Kothandaraman","year":"2002","unstructured":"Kothandaraman C, Iyer SK, Iyer SS (2002) Electrically programmable fuse (eFUSE) using electromigration in silicides. IEEE Electron Device Lett 23(9):523\u2013525","journal-title":"IEEE Electron Device Lett"},{"key":"5001_CR17","unstructured":"Kumar SV, Kim CH, Sapatnekar SS (2006) Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. In: Asia and south pacific conference on design automation, IEEE, 559\u2013564 January 2006"},{"issue":"2","key":"5001_CR18","doi-asserted-by":"crossref","first-page":"210","DOI":"10.1109\/4.982427","volume":"37","author":"M Miyazaki","year":"2002","unstructured":"Miyazaki M, Ono G, Ishibashi K (2002) A 1.2-GIPS\/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. IEEE J Solid-State Circuits 37(2):210\u2013217","journal-title":"IEEE J Solid-State Circuits"},{"issue":"8","key":"5001_CR19","doi-asserted-by":"crossref","first-page":"847","DOI":"10.1109\/4.400426","volume":"30","author":"S Mutoh","year":"1995","unstructured":"Mutoh S, Douseki T, Matsuya Y, Aoki T, Shigematsu S, Yamada J (1995) 1-V power supply high-speed digital ciruit technology with multithreshold-voltage CMOS. IEEE J Solid-State Circuits 30(8):847\u2013853","journal-title":"EEE J Solid-State Circuits"},{"key":"5001_CR20","doi-asserted-by":"crossref","unstructured":"Nassif SR (2000) Modeling and forecasting of manufacturing variations. In: International workshop on statistical metrology, IEEE, 2\u201310 June 2000","DOI":"10.1109\/IWSTM.2000.869299"},{"key":"5001_CR21","doi-asserted-by":"crossref","unstructured":"Shepard KL, Narayanan V (1996) Noise in deep submicron digital design. In: International conference on computer-aided design, IEEE, 524\u2013531 November 1996","DOI":"10.1109\/ICCAD.1996.569906"},{"issue":"4","key":"5001_CR22","doi-asserted-by":"crossref","first-page":"536","DOI":"10.1109\/4.753687","volume":"34","author":"V Stojanovic","year":"1999","unstructured":"Stojanovic V, Oklobdzija V (1999) Comparative analysis of master-slave latches and flip-flops for high-performance and low power systems. IEEE J Solid-State Circuits 34(4):536\u2013548","journal-title":"IEEE J Solid-State Circuits"},{"key":"5001_CR23","unstructured":"Synopsis Inc. (2000) Primetime Reference - Version 2000.11 (November)"},{"issue":"4","key":"5001_CR24","doi-asserted-by":"crossref","first-page":"636","DOI":"10.1109\/JSSC.2004.825121","volume":"39","author":"S Tam","year":"2004","unstructured":"Tam S, Limaye RD, Desai UN (2004) Clock generation and distribution for the 130-nm itanium 2 processor with 6-MB on-die L3 cache. IEEE J Solid-State Circuits 39(4):636\u2013642","journal-title":"IEEE J Solid-State Circuits"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-007-5001-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-007-5001-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-007-5001-y","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T21:57:42Z","timestamp":1559253462000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-007-5001-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1,4]]},"references-count":24,"journal-issue":{"issue":"1-3","published-print":{"date-parts":[[2008,6]]}},"alternative-id":["5001"],"URL":"https:\/\/doi.org\/10.1007\/s10836-007-5001-y","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,1,4]]}}}