{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T13:18:14Z","timestamp":1648559894665},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"1-3","license":[{"start":{"date-parts":[[2008,1,17]],"date-time":"2008-01-17T00:00:00Z","timestamp":1200528000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1007\/s10836-007-5023-5","type":"journal-article","created":{"date-parts":[[2008,1,16]],"date-time":"2008-01-16T21:59:34Z","timestamp":1200520774000},"page":"165-179","source":"Crossref","is-referenced-by-count":4,"title":["Defect Analysis and Defect Tolerant Design of Multi-port SRAMs"],"prefix":"10.1007","volume":"24","author":[{"given":"Lushan","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pradeep","family":"Nagaraj","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shambhu","family":"Upadhyaya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramalingam","family":"Sridhar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2008,1,17]]},"reference":[{"key":"5023_CR1","unstructured":"Adams RD (1996) Extensions of static random access memories, fault modeling and examination of patterns for fault detection. Masters Thesis, Dartmouth College"},{"key":"5023_CR2","doi-asserted-by":"crossref","unstructured":"Al-Ars Z, van de Goor AJ (2001) Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. In: Proceedings of Design, Automation and Test in Europe, Munich, 13\u201316 March 2001, pp 496\u2013503","DOI":"10.1109\/DATE.2001.915069"},{"key":"5023_CR3","doi-asserted-by":"crossref","unstructured":"Baker K, Gronthoud G, Lousberg M, Schanstra I, Hawkins C (1999) Defect-based delay testing of resistive vias-contacts a critical evaluation. In: Proceedings of International Test Conference. IEEE, Piscataway, pp 467\u2013476","DOI":"10.1109\/TEST.1999.805769"},{"key":"5023_CR4","doi-asserted-by":"crossref","unstructured":"Chandrakasan A, Bowhill WJ, Fox F (2000) Design of high-performance microprocessor circuits. IEEE, Piscataway","DOI":"10.1109\/9780470544365"},{"key":"5023_CR5","unstructured":"Cypress Semiconductor (2007) Understanding specialty memories: dual-port RAM. Technical article. http:\/\/www.cypress.com\/"},{"key":"5023_CR6","doi-asserted-by":"crossref","unstructured":"Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Borri S, Bastian Hage-Hassan M (2004) Resistive-open defects in embedded-SRAM core cells: analysis and march test solution. Test Symposium, Asian. IEEE, Piscataway, pp 266\u2013271","DOI":"10.1109\/ATS.2004.75"},{"key":"5023_CR7","doi-asserted-by":"crossref","unstructured":"Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Borri S, Hage-Hassan M (2004) Dynamic read destructive fault in embedded-SRAMs: Analysis and march test solutions. Proceedings of the IEEE European Test Symposium. IEEE, Piscataway, pp 140\u2013145","DOI":"10.1109\/ETSYM.2004.1347645"},{"key":"5023_CR8","doi-asserted-by":"crossref","unstructured":"Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2005) Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13\u00a0\u03bcm and 90\u00a0nm technologies. Proceedings of Design Automation Conference. IEEE, Piscataway, pp 857\u2013862","DOI":"10.1145\/1065579.1065804"},{"key":"5023_CR9","doi-asserted-by":"crossref","unstructured":"Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Bastian Hage-Hassan M (2005) Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. European Test Symposium. IEEE, Piscataway, pp 116\u2013121","DOI":"10.1109\/ETS.2005.33"},{"key":"5023_CR10","doi-asserted-by":"crossref","unstructured":"Gieseke B et al (1997) A 600\u00a0MHz superscalar RISC microprocessor with out-of-order execution. Paper 10.7 ISSCC Digest of Technical Papers, pp 176\u2013177","DOI":"10.1109\/ISSCC.1997.585323"},{"key":"5023_CR11","unstructured":"Hamdioui, S, van de Goor AJ (1998) Fault models and tests for two-port memories. Proceedings of IEEE VLSI Test Symposium. IEEE, Piscataway, pp 401\u2013410"},{"key":"5023_CR12","doi-asserted-by":"crossref","unstructured":"Hamdioui, S, van de Goor AJ (1998) Consequences of port restrictions on testing two-port memories. Proceedings of International Test Conference. IEEE, Piscataway, pp 63\u201372","DOI":"10.1109\/TEST.1998.743138"},{"key":"5023_CR13","doi-asserted-by":"crossref","unstructured":"Hamdioui S, van de Goor AJ (1999) Port interference faults in two-port memories. Proceedings of IEEE International Test Conference. IEEE, Piscataway, pp 1001\u20131010","DOI":"10.1109\/TEST.1999.805833"},{"key":"5023_CR14","doi-asserted-by":"crossref","unstructured":"Hamdioui S, van de Goor AJ, Eastwick D, Rodgers M (2001) Realistic fault models and test procedure for multi-port SRAMs. IEEE International Workshop on Memory Technology, Design and Testing. IEEE, Piscataway, pp 65\u201372","DOI":"10.1109\/MTDT.2001.945230"},{"key":"5023_CR15","doi-asserted-by":"crossref","unstructured":"Nagaraj P, Upadhyaya S, Zarrineh K, Adams D (2001) Defect analysis and a new fault model for multi-port SRAMs. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE, Piscataway, pp 366\u2013374","DOI":"10.1109\/DFTVS.2001.966790"},{"key":"5023_CR16","doi-asserted-by":"crossref","unstructured":"Needham W et al (1998) High volume microprocessor test escapes\u2014an analysis of defects our tests are missing. Proceedings of the International Test Conference. IEEE, Piscataway, pp 25\u201334","DOI":"10.1109\/TEST.1998.743133"},{"key":"5023_CR17","doi-asserted-by":"crossref","unstructured":"Park I, Powell M, Vijaykumar T (2002) Reducing register ports for higher speed and lower energy. Proceedings of 35th Annual IEEE\/ACM International Symposium on Microarchitecture, 2002 (MICRO-35), Istanbul, 18\u201322 November 2002","DOI":"10.1109\/MICRO.2002.1176248"},{"key":"5023_CR18","doi-asserted-by":"crossref","unstructured":"Powell TJ, Cheng W-T, Rayhawk J, Samman O, Policke P, Lai S (2003) BIST for deep submicron asic memories with high performance application. Proceedings of IEEE ITC, International Test Conference. IEEE, Piscataway, pp 386\u2013392","DOI":"10.1109\/TEST.2003.1270862"},{"key":"5023_CR19","unstructured":"Rabaey J, Chandrakasan A, Nikolic B (2003) Digital integrated circuits: a design perspective, 2nd edn. Prentice-Hall, Englewood Cliffs"},{"key":"5023_CR20","doi-asserted-by":"crossref","first-page":"741","DOI":"10.1109\/TC.2005.88","volume":"54","author":"K Tseng","year":"2006","unstructured":"Tseng K, Asanovic JH (2006) A speculative control scheme for an energy-efficient banked register file. IEEE Trans Comput 54:741\u2013751","journal-title":"IEEE Trans Comput"},{"key":"5023_CR21","volume-title":"Testing semiconductors memories, theory and practice","author":"AJ Goor van de","year":"1998","unstructured":"van de Goor AJ (1998) Testing semiconductors memories, theory and practice. ComTex, Gouda"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-007-5023-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-007-5023-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-007-5023-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,31]],"date-time":"2019-05-31T01:57:42Z","timestamp":1559267862000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-007-5023-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1,17]]},"references-count":21,"journal-issue":{"issue":"1-3","published-print":{"date-parts":[[2008,6]]}},"alternative-id":["5023"],"URL":"https:\/\/doi.org\/10.1007\/s10836-007-5023-5","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,1,17]]}}}