{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:18:50Z","timestamp":1761675530018},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"1-3","license":[{"start":{"date-parts":[[2008,1,10]],"date-time":"2008-01-10T00:00:00Z","timestamp":1199923200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1007\/s10836-007-5027-1","type":"journal-article","created":{"date-parts":[[2008,1,9]],"date-time":"2008-01-09T10:42:13Z","timestamp":1199875333000},"page":"157-163","source":"Crossref","is-referenced-by-count":4,"title":["Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy"],"prefix":"10.1007","volume":"24","author":[{"given":"Kristian","family":"Granhaug","sequence":"first","affiliation":[]},{"given":"Snorre","family":"Aunet","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2008,1,10]]},"reference":[{"issue":"2","key":"5027_CR1","doi-asserted-by":"crossref","first-page":"205","DOI":"10.1109\/72.80331","volume":"2","author":"AG Andreou","year":"1991","unstructured":"Andreou AG, Boahen KA, Pouliquen PO, Pavasovi\u0107 A, Jenkins RE, Strohbehn K (1991) Current-mode subthreshold MOS circuits for analog VLSI neural systems. IEEE Trans Neural Netw 2(2):205\u2013213, March","journal-title":"IEEE Trans Neural Netw"},{"key":"5027_CR2","doi-asserted-by":"crossref","unstructured":"Aunet S, Beiu V (2005) Ultra low power fault tolerant neural inspired CMOS logic. IEEE International Joint Conference on Neural Networks, IJCNN, Montr\u00e9al, Canada, July 31\u2013August 4, 2005","DOI":"10.1109\/IJCNN.2005.1556376"},{"key":"5027_CR3","unstructured":"Aunet S, Berg Y (2005) Three sub-fJ power-delay-product subthreshold CMOS gates. IFIP VLSI SoC, Perth, Australia, 17\u201319 October 2005"},{"key":"5027_CR4","doi-asserted-by":"crossref","unstructured":"Aunet S, Hartmann M (2003) Real-time reconfigurable linear threshold elements and some applications to neural hardware. International Conference on Evolvable Systems, ICES 2003, Trondheim, Norway, 17\u201320 March 2003","DOI":"10.1007\/3-540-36553-2_33"},{"key":"5027_CR5","doi-asserted-by":"crossref","unstructured":"Aunet S, Oelmann B, Abdalla S, Berg Y (2004) Reconfigurable subthreshold CMOS perceptron. International Joint Conference on Neural Networks, IJCNN, Budapest, Hungary, 25\u201329 July 2004","DOI":"10.1109\/IJCNN.2004.1380919"},{"key":"5027_CR6","doi-asserted-by":"crossref","unstructured":"Beiu V, Aunet S, Rydberg III RR, Djupdal A (2005) On the advantages of serial architectures for low-power reliable computations. Proceedings of the 16th International Conference on Application-Specific Systems, Architecture and Processors, ASAP\u201905, Samos, Greece, 23\u201325 July 2005","DOI":"10.1109\/ASAP.2005.48"},{"key":"5027_CR7","doi-asserted-by":"crossref","unstructured":"Bryant A, Brown J, Cottrell P, Ketchen M, Ellis-Monaghan J, Nowak EJ (2001) Low-Power CMOS at Vdd=4kT\/q. Dev Res Conf 2001","DOI":"10.1109\/DRC.2001.937856"},{"key":"5027_CR8","unstructured":"Closing the nanometer yield chasm, cadence design systems. White Paper, 2001. Available: www.cadence.com\/whitepapers\/ClosingNanometer061301.pdf"},{"issue":"4","key":"5027_CR9","doi-asserted-by":"crossref","first-page":"360","DOI":"10.1109\/92.645062","volume":"5","author":"M Eisele","year":"1997","unstructured":"Eisele M, Berthold J, Schmitt-Landsiedel D, Mahnkopf R (1997) The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Transactions Very Large Scale Integr (VLSI) Syst 5(4):360\u2013368, December","journal-title":"IEEE Transactions Very Large Scale Integr (VLSI) Syst"},{"key":"5027_CR10","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1007\/BF01239381","volume":"8","author":"CC Enz","year":"1995","unstructured":"Enz CC, Krummenacher F, Vittoz EA (1995) An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integr Circuits Signal Process 8:83\u2013114, July","journal-title":"Analog Integr Circuits Signal Process"},{"key":"5027_CR11","doi-asserted-by":"crossref","unstructured":"Enz CC, Vittoz EA (1996) CMOS low-power analog circuit design. In: Cavin et al (eds) Emerging technologies: designing low power digital systems. IEEE Press","DOI":"10.1109\/ETLPDS.1996.508872"},{"key":"5027_CR12","doi-asserted-by":"crossref","unstructured":"Granhaug K, Aunet S, Lande TS (2006) Body-bias regulator for ultra low power multifunction CMOS gates. International Symposium of Circuits and Systems, ISCAS 2006, Kos, Greece, 21\u201324 May 2006","DOI":"10.1109\/ISCAS.2006.1692820"},{"key":"5027_CR13","unstructured":"Iwamura H, Akazawa M, Amemiya Y (1998) Single electron majority logic circuits. IEICE Transac Electron, V E18 C, pp 42\u201348"},{"issue":"11","key":"5027_CR14","doi-asserted-by":"crossref","first-page":"1545","DOI":"10.1109\/JSSC.2002.803957","volume":"37","author":"JT Kao","year":"2002","unstructured":"Kao JT, Miyazaki M, Chandrakasan AP (2002) A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture. IEEE J Solid-State Circuits 37(11):1545\u20131554, November 2002","journal-title":"IEEE J Solid-State Circuits"},{"key":"5027_CR15","unstructured":"Lehtonen T, Plosila J, Isoaho J (2005) On fault tolerance techniques towards nanoscale circuits and systems. TUCS Technical Report, no. 708, August 2005"},{"issue":"9","key":"5027_CR16","doi-asserted-by":"crossref","first-page":"1528","DOI":"10.1109\/PROC.1969.7331","volume":"57","author":"F Leuenberger","year":"1969","unstructured":"Leuenberger F, Vittoz E (1969) Complementary-MOS low-power low-voltage integrated binary counter. Proceedings of the IEEE 57(9):1528\u20131532, September","journal-title":"Proceedings of the IEEE"},{"key":"5027_CR17","unstructured":"Lin X, Rajski J (2006) The impacts of untestable defects on transition fault testing. Proceedings of the 24th IEEE VLSI Test Symposium, VTS\u201906, Berkeley, CA, USA, 30 April\u20134 May 2006"},{"key":"5027_CR18","doi-asserted-by":"crossref","unstructured":"Melek LAP, Schneider MC, Galup-Montoro C (2004) Body-bias compensation technique for subthreshold CMOS static logic gates. SBCCI\u201904, Ipojuca, Brazil, 7\u201311 September 2004","DOI":"10.1145\/1016568.1016639"},{"issue":"8","key":"5027_CR19","first-page":"114","volume":"38","author":"G Moore","year":"1965","unstructured":"Moore G (1965) Cramming more components onto integrated circuits. Electronics 38(8):114\u2013117","journal-title":"Electronics"},{"key":"5027_CR20","doi-asserted-by":"crossref","first-page":"357","DOI":"10.1088\/0957-4484\/13\/3\/323","volume":"13","author":"K Nikoli\u0107","year":"2002","unstructured":"Nikoli\u0107 K, Sadek A, Forshaw M (2002) Fault-tolerant techniques for nanocomputers. Nanotechnology 13:357\u2013362, June","journal-title":"Nanotechnology"},{"issue":"2\/3","key":"5027_CR21","doi-asserted-by":"crossref","first-page":"169","DOI":"10.1147\/rd.462.0169","volume":"46","author":"EJ Nowak","year":"2002","unstructured":"Nowak EJ (2002) Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J Res Dev 46(2\/3):169\u2013180, March\/May","journal-title":"IBM J Res Dev"},{"key":"5027_CR22","volume-title":"Low power design methodologies","author":"J Rabaey","year":"1995","unstructured":"Rabaey J, Pedram M, Landman P (1995) Low power design methodologies. Kluwer, Boston, 1995"},{"key":"5027_CR23","doi-asserted-by":"crossref","unstructured":"Schmid A, Leblebici Y (2003) Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. Third IEEE Conference on Nanotechnology, IEEE-NANO, San Francisco, CA, USA, 12\u201314 August 2003","DOI":"10.1109\/NANO.2003.1230960"},{"key":"5027_CR24","doi-asserted-by":"crossref","unstructured":"Schrom G, Selberherr S (1996) Ultra-low-power CMOS technologies. International Semiconductor Conference, CAS\u201996, Sinaia, Romania","DOI":"10.1109\/SMICND.1996.557352"},{"issue":"3","key":"5027_CR25","doi-asserted-by":"crossref","first-page":"870","DOI":"10.1109\/4.102688","volume":"25","author":"K Schultz","year":"1990","unstructured":"Schultz K, Francis RJ, Smith KC (1990) Ganged CMOS: trading standby power for speed. IEEE J Solid-State Circuits 25(3):870\u2013873, June","journal-title":"IEEE J Solid-State Circuits"},{"key":"5027_CR26","doi-asserted-by":"crossref","unstructured":"Shibata T, Ohmi T (1991) An intelligent MOS transistor featuring gate-level weighted sum and threshold operations. Technical Digest of International Electron Devices Meeting, pp 919\u2013922","DOI":"10.1109\/IEDM.1991.235276"},{"issue":"1","key":"5027_CR27","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/92.920822","volume":"9","author":"H Soeleman","year":"2001","unstructured":"Soeleman H, Roy K, Paul, BC (2001) Robust subthreshold logic for ultra-low power operation. IEEE Transac Very Large Scale Integr (VLSI) Syst 9(1):90\u201399, Febuary","journal-title":"IEEE Transac Very Large Scale Integr (VLSI) Syst"},{"issue":"2","key":"5027_CR28","doi-asserted-by":"crossref","first-page":"146","DOI":"10.1109\/JSSC.1972.1050260","volume":"7","author":"RM Swanson","year":"1972","unstructured":"Swanson RM, Meindl JD (1972) Ion-implanted complementary MOS transistors in low-voltage circuits. IEEE J Solid-State Circuits 7(2):146\u2013153, April","journal-title":"IEEE J Solid-State Circuits"},{"key":"5027_CR29","first-page":"43","volume-title":"Automata Studies","author":"J Neumann von","year":"1956","unstructured":"von Neumann J (1956) Probabilistic logics and the synthesis of reliable organisms from unreliable components. In: Shannon CE, McCarthy J (eds) Automata Studies. Princeton Univ. Press, Princeton, NJ, pp 43\u201398"},{"issue":"1","key":"5027_CR30","doi-asserted-by":"crossref","first-page":"310","DOI":"10.1109\/JSSC.2004.837945","volume":"40","author":"A Wang","year":"2005","unstructured":"Wang A, Chandrakasan A (2005) A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J Solid-State Circuits 40(1):310\u2013319, January","journal-title":"IEEE J Solid-State Circuits"},{"key":"5027_CR31","unstructured":"Weste N, Harris D (2004) CMOS VLSI design\u2014a circuits and systems perspective, 3rd edn. Addison-Wesley"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-007-5027-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-007-5027-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-007-5027-1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T21:57:42Z","timestamp":1559253462000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-007-5027-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1,10]]},"references-count":31,"journal-issue":{"issue":"1-3","published-print":{"date-parts":[[2008,6]]}},"alternative-id":["5027"],"URL":"https:\/\/doi.org\/10.1007\/s10836-007-5027-1","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,1,10]]}}}