{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,30]],"date-time":"2025-01-30T21:10:22Z","timestamp":1738271422894,"version":"3.35.0"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2008,6,24]],"date-time":"2008-06-24T00:00:00Z","timestamp":1214265600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2008,12]]},"DOI":"10.1007\/s10836-008-5072-4","type":"journal-article","created":{"date-parts":[[2008,6,23]],"date-time":"2008-06-23T20:33:58Z","timestamp":1214253238000},"page":"577-590","source":"Crossref","is-referenced-by-count":4,"title":["Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique"],"prefix":"10.1007","volume":"24","author":[{"given":"Swarup","family":"Bhunia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Mahmoodi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arijit","family":"Raychowdhury","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2008,6,24]]},"reference":[{"issue":"3","key":"5072_CR1","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1109\/TVLSI.2004.842885","volume":"13","author":"S Bhunia","year":"2005","unstructured":"Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Trans Very Large Scale Integr Syst 13(3):384\u2013395, Mar","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5072_CR2","doi-asserted-by":"crossref","unstructured":"Borkar S, et al (2003) Parameter variations and impact on circuits and microarchitecture. Design Automation Conference, pp 338\u2013342","DOI":"10.1145\/775832.775920"},{"key":"5072_CR3","volume-title":"Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits","author":"ML Bushnell","year":"2000","unstructured":"Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer, Boston"},{"key":"5072_CR4","doi-asserted-by":"crossref","unstructured":"Calhoun BH, Honore FA, Chandrakasan A (2003) Design methodology for fine-grained leakage control in MTCMOS. In: International symposium on low power electronics design, Seoul, pp 104\u2013107, 25\u201327 August","DOI":"10.1145\/871506.871535"},{"key":"5072_CR5","unstructured":"Cheng K-T, Devadas S, Keutzer K (1991) A partial en- hanced scan approach to robust delay-fault test generation for sequential circuits. In: International test conference, Nashville, pp 403\u2013410, 26\u201330 October"},{"key":"5072_CR6","doi-asserted-by":"crossref","unstructured":"DasGupta S, Eichelberger EB, Williams TW (1978) LSI chip design for testability, digest of technical papers. In: IEEE international solid-state circuits conference, IEEE, Piscataway, pp 216\u2013217, Feb","DOI":"10.1109\/ISSCC.1978.1155765"},{"key":"5072_CR7","unstructured":"DasGupta S, Walther RG, Williams TW, Eichelberger EB (1981) An enhancement to LSSD and some applications of LSSD in reliability, availability, and serviceability. In: International symposium on fault-tolerant computing, Portland, pp 32\u201334, June"},{"key":"5072_CR8","doi-asserted-by":"crossref","unstructured":"Dervisoglu BI, Stong GE (1991) Design for testability: using scanpath techniques for path-delay test and measurement. In: International test conference, Nashville, pp 365\u2013374, 26\u201330 October","DOI":"10.1109\/TEST.1991.519696"},{"key":"5072_CR9","unstructured":"EETimes (2002) EEDesign Article. Delay-fault testing mandatory, author claims. http:\/\/www.eedesign.com\/story\/OEG20021204S0029 , Dec"},{"key":"5072_CR10","unstructured":"EETimes (2002) EETimes Article. Researchers: time to overhaul design. http:\/\/www.eetimes.com\/showArticle.jhtml?articleID=18307867 , Dec"},{"key":"5072_CR11","unstructured":"EETimes (2003) EETimes Article. Scan-based transition-fault test can do job. http:\/\/www.eetimes.com\/story\/OEG20031024S0028 , Oct"},{"key":"5072_CR12","doi-asserted-by":"crossref","unstructured":"Gerstendrfer S, Wunderlich H-J (1999) Minimized power consumption for scan-based BIST. In: International test conference, Atlantic City, pp 77\u201384, 27\u201330 September","DOI":"10.1109\/TEST.1999.805616"},{"key":"5072_CR13","doi-asserted-by":"crossref","unstructured":"Jahangiri J, Abercrombie D (2005) Meeting nanometer DPM requirements through DFT. In: International symposium on quality of electronic design, San Jose, pp 276\u2013282, 21\u201323 March","DOI":"10.1109\/ISQED.2005.76"},{"key":"5072_CR14","unstructured":"Kuppuswamy R et al (2004) Full hold-scan systems in microprocessors: cost\/benefit analysis. Intel Technol J 8(1), Feb"},{"issue":"5","key":"5072_CR15","doi-asserted-by":"crossref","first-page":"638","DOI":"10.1109\/43.277638","volume":"13","author":"W Mao","year":"1994","unstructured":"Mao W, Ciletti MD (1994) Reducing correlation to improve coverage of delay faults in scan-path design. IEEE Trans Comput-aided Des Integr Circuits Syst 13(5):638\u2013646, May","journal-title":"IEEE Trans Comput-aided Des Integr Circuits Syst"},{"key":"5072_CR16","doi-asserted-by":"crossref","unstructured":"Ohtake S, Miwa S, Fujiwara H (2002) A method of test generation for path delay faults in balanced sequential circuits. In: VLSI test symposium, Monterey, pp 321\u2013327, 28 April\u20132 May","DOI":"10.1109\/VTS.2002.1011160"},{"key":"5072_CR17","doi-asserted-by":"crossref","unstructured":"Rearick J (2001) Too much delay fault coverage is a bad thing. In: International test conference, Baltimore, pp 624\u2013633, 30 October\u20131 November","DOI":"10.1109\/TEST.2001.966682"},{"key":"5072_CR18","doi-asserted-by":"crossref","first-page":"305","DOI":"10.1109\/JPROC.2002.808156","volume":"91","author":"K Roy","year":"2003","unstructured":"Roy K, Mukhopadhyay S, Mahmoodi-Meimand H (2003) Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc IEEE 91:305\u2013327, Feb","journal-title":"Proc IEEE"},{"key":"5072_CR19","doi-asserted-by":"crossref","unstructured":"Savir J (1997) Scan latch design for delay test. In: International test conference, Washington, DC, pp 446\u2013452, 3\u20135 November","DOI":"10.1109\/TEST.1997.639650"},{"key":"5072_CR20","doi-asserted-by":"crossref","unstructured":"TekuMalla RC, Menon PR (1997) Delay testing with clock control: an alternative to enhanced scan. In: International test conference, Washington, DC, pp 454\u2013462, 3\u20135 November","DOI":"10.1109\/TEST.1997.639651"},{"key":"5072_CR21","unstructured":"University of California (2001) Predictive technology model. http:\/\/www-device.eecs.berkeley.edu\/~ptm"},{"key":"5072_CR22","unstructured":"Wang S, Liu X, Chakradhar ST (2004) Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets. In: Design automation and test in Europe, Paris, pp 1296\u20131301, 16\u201320 February"},{"key":"5072_CR23","unstructured":"Warnock JD, Huott WV (2005) High-speed level sensitive scan design test scheme with pipelined test clocks. United States Patent 7178075 B2"},{"key":"5072_CR24","unstructured":"Zhang A (2006) Modeling custom scan flops in level sensitive scan design. United States Patent 7039843"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-008-5072-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-008-5072-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-008-5072-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,30]],"date-time":"2025-01-30T20:52:56Z","timestamp":1738270376000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-008-5072-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6,24]]},"references-count":24,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2008,12]]}},"alternative-id":["5072"],"URL":"https:\/\/doi.org\/10.1007\/s10836-008-5072-4","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2008,6,24]]}}}