{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,20]],"date-time":"2024-08-20T12:30:51Z","timestamp":1724157051047},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"4-5","license":[{"start":{"date-parts":[[2009,7,29]],"date-time":"2009-07-29T00:00:00Z","timestamp":1248825600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2009,8]]},"DOI":"10.1007\/s10836-009-5109-3","type":"journal-article","created":{"date-parts":[[2009,7,28]],"date-time":"2009-07-28T08:59:34Z","timestamp":1248771574000},"page":"259-268","source":"Crossref","is-referenced-by-count":19,"title":["Adaptive Debug and Diagnosis Without Fault Dictionaries"],"prefix":"10.1007","volume":"25","author":[{"given":"Stefan","family":"Holst","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2009,7,29]]},"reference":[{"key":"5109_CR1","doi-asserted-by":"crossref","unstructured":"Abramovici M, Breuer MA (1980) Fault diagnosis based on effect-cause analysis: an introduction. In: 17th conference on design automation, pp 69\u201376","DOI":"10.1145\/800139.804514"},{"key":"5109_CR2","doi-asserted-by":"crossref","unstructured":"Amyeen ME, Nayak D, Venkataraman S (2006) Improving precision using mixed-level fault diagnosis. In: Proceedings IEEE international test conference 2006, Santa Clara, 24\u201326 October 2006, p 22.3","DOI":"10.1109\/TEST.2006.297661"},{"key":"5109_CR3","doi-asserted-by":"crossref","unstructured":"Arnaout T, Bartsch G, Wunderlich H-J (2006) Some common aspects of design validation, debug and diagnosis. In: Third IEEE international workshop on electronic design, test and applications (DELTA 2006), Kuala Lumpur, 17\u201319 January 2006, pp 3\u201310","DOI":"10.1109\/DELTA.2006.79"},{"key":"5109_CR4","doi-asserted-by":"crossref","unstructured":"Bartenstein T (2000) Fault distinguishing pattern generation. In: Proceedings IEEE international test conference 2000, Atlantic City, pp 820\u2013828","DOI":"10.1109\/TEST.2000.894285"},{"key":"5109_CR5","doi-asserted-by":"crossref","unstructured":"Bartenstein T, Heaberlin D, Huisman LM, Sliwinski D (2001) Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. In: Proceedings IEEE international test conference 2001, Baltimore, 30 October\u20131 November 2001, pp 287\u2013296","DOI":"10.1109\/TEST.2001.966644"},{"key":"5109_CR6","doi-asserted-by":"crossref","unstructured":"Bhatti NK, Blanton RS (2006) Diagnostic test generation for arbitrary faults. In: Proceedings IEEE international test conference 2006, Santa Clara, 24\u201326 October, 2006, p 19.2","DOI":"10.1109\/TEST.2006.297647"},{"key":"5109_CR7","doi-asserted-by":"crossref","unstructured":"Boppana V, Fujita M (1998) Modeling the unknown! towards model-independent fault and error diagnosis. In: Proceedings IEEE international test conference 1998, Washington, DC, 18\u201322 October 1998, pp 1094\u20131100","DOI":"10.1109\/TEST.1998.743310"},{"key":"5109_CR8","doi-asserted-by":"crossref","unstructured":"Boppana V, Hartanto I, Fuchs WK (1996) Full fault dictionary storage based on labeled tree encoding. In: 14th IEEE VLSI test symposium (VTS\u201996), Princeton, 28 April\u20131 May 1996, pp 174\u2013179","DOI":"10.1109\/VTEST.1996.510854"},{"key":"5109_CR9","unstructured":"Chen KC (2003) Assertion-based verification for SoC designs. In: Proceedings 5th international conference on ASIC, vol 1, pp 12\u201315"},{"issue":"3","key":"5109_CR10","doi-asserted-by":"crossref","first-page":"346","DOI":"10.1109\/43.748164","volume":"18","author":"B Chess","year":"1999","unstructured":"Chess B, Larrabee T (1999) Creating small fault dictionaries. IEEE Trans Comput-aided Des Integr Circuits Syst 18(3):346\u2013356","journal-title":"IEEE Trans Comput-aided Des Integr Circuits Syst"},{"key":"5109_CR11","doi-asserted-by":"crossref","unstructured":"Chess B, Lavo DB, Ferguson FJ, Larrabee T (1995) Diagnosis of realistic bridging faults with single stuck-at information. In: Proceedings of the 1995 IEEE\/ACM international conference on computer-aided design, 1995, San Jose, 5\u20139 November 1995, pp 185\u2013192","DOI":"10.1109\/ICCAD.1995.480011"},{"key":"5109_CR12","doi-asserted-by":"crossref","unstructured":"Desineni R, Poku O, Blanton RDS (2006) A logic diagnosis methodology for improved localization and extraction of accurate defect behavior. In: Proceedings IEEE international test conference 2006, Santa Clara, 24\u201326 October 2006, p 12.3","DOI":"10.1109\/TEST.2006.297627"},{"key":"5109_CR13","unstructured":"Fan X, Moore W, Hora C, Gronthoud G (2005) Stuck-open fault diagnosis with stuck-at model. In: Proceedings European test symposium, Tallin, pp 182\u2013187"},{"key":"5109_CR14","unstructured":"Fitzpatrick T (2005) Realizing advanced functional verification with questa. Mentor Graphics Corporation (white paper)"},{"key":"5109_CR15","doi-asserted-by":"crossref","unstructured":"Gong Y, Chakravarty S (1995) On adaptive diagnostic test generation. In: Proceedings IEEE international conference on computer-aided design, p 181","DOI":"10.1109\/ICCAD.1995.480010"},{"key":"5109_CR16","unstructured":"Henderson CL, Soden JM (1997) Signature analysis for ic diagnosis and failure analysis. In: Proceedings IEEE international test conference 1997, Washington, DC, 3\u20135 November 1997, pp 310\u2013318"},{"key":"5109_CR17","doi-asserted-by":"crossref","unstructured":"Holst S, Wunderlich H-J (2007) Adaptive debug and diagnosis without fault dictionaries. In: 12th European test symposium (ETS 2007), 20 May 2007, Freiburg, pp 7\u201312","DOI":"10.1109\/ETS.2007.9"},{"key":"5109_CR18","doi-asserted-by":"crossref","unstructured":"Hora C, Segers R, Eichenberger S, Lousberg M (2002) An effective diagnosis method to support yield improvement. In: Proceedings IEEE international test conference 2002, Baltimore, 7\u201310 October 2002, pp 260\u2013269","DOI":"10.1109\/TEST.2002.1041768"},{"issue":"1","key":"5109_CR19","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1109\/TCAD.2003.816206","volume":"23","author":"LM Huisman","year":"2004","unstructured":"Huisman LM (2004) Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans Comput-aided Des Integr Circuits Syst 23(1):91\u2013101","journal-title":"IEEE Trans Comput-aided Des Integr Circuits Syst"},{"key":"5109_CR20","doi-asserted-by":"crossref","unstructured":"Klein R, Piekarz T (2005) Accelerating functional simulation for processor based designs. Mentor Graphics Corporation (white paper)","DOI":"10.1109\/IWSOC.2005.34"},{"key":"5109_CR21","doi-asserted-by":"crossref","unstructured":"Krstic A, Wang L-C, Cheng K-T, Liou J-J, Abadir MS (2003) Delay defect diagnosis based upon statistical timing models\u2014the first step. In: 2003 design, automation and test in Europe conference and exposition (DATE 2003), Munich, 3\u20137 March 2003, pp 10328\u201310335","DOI":"10.1049\/ip-cdt:20030834"},{"key":"5109_CR22","doi-asserted-by":"crossref","unstructured":"Lavo DB, Chess B, Larrabee T, Hartanto I (1998) Probabilistic mixed-model fault diagnosis. In: Proceedings IEEE international test conference 1998, Washington, DC, 18\u201322 October 1998, pp 1084\u20131093","DOI":"10.1109\/TEST.1998.743308"},{"key":"5109_CR23","doi-asserted-by":"crossref","unstructured":"McPherson JW (2006) Reliability challenges for 45nm and beyond. In: Proceedings of the 43rd design automation conference, DAC 2006, San Francisco, 24\u201328 July 2006, pp 176\u2013181","DOI":"10.1145\/1146909.1146959"},{"key":"5109_CR24","doi-asserted-by":"crossref","unstructured":"Millman SD, McCluskey EJ, Acken JM (1990) Diagnosing CMOS bridging faults with stuck-at fault dictionaries. In: Proceedings IEEE international test conference, pp 860\u2013870","DOI":"10.1109\/TEST.1990.114104"},{"key":"5109_CR25","doi-asserted-by":"crossref","unstructured":"Pomeranz I, Reddy SM (1992) On the generation of small dictionaries for fault location. In: IEEE\/ACM international conference on computer-aided design, ICCAD92, Santa Clara, 8\u201312 November 1992, pp 272\u2013279","DOI":"10.1109\/ICCAD.1992.279361"},{"key":"5109_CR26","doi-asserted-by":"crossref","unstructured":"Renovell M, Huc P, Bertrand Y (1994) CMOS bridging fault modeling. In: 12th IEEE VLSI test symposium (VTS), 25\u201328 Apr 1994, pp 392\u2013297","DOI":"10.1109\/VTEST.1994.292283"},{"key":"5109_CR27","doi-asserted-by":"crossref","unstructured":"Riley M, Chelstrom N, Genden M, Sawamura S (2006) Debug of the CELL processor: moving the lab into silicon. In: Proceedings IEEE international test conference 2006, Santa Clara, 24\u201326 October 2006, p 26.1","DOI":"10.1109\/TEST.2006.297671"},{"issue":"2","key":"5109_CR28","doi-asserted-by":"crossref","first-page":"128","DOI":"10.1109\/MDT.2006.52","volume":"23","author":"K Roy","year":"2006","unstructured":"Roy K, Mak TM, Cheng K-TT (2006) Test consideration for nanometer-scale cmos circuits. IEEE Des Test Comput 23(2):128\u2013136","journal-title":"IEEE Des Test Comput"},{"key":"5109_CR29","doi-asserted-by":"crossref","first-page":"73","DOI":"10.1023\/A:1021948013402","volume":"19","author":"R Ubar","year":"2003","unstructured":"Ubar R (2003) Design error diagnosis with resynthesis in combinational circuits. J Electron Test Theory Appl 19:73\u201382","journal-title":"J Electron Test Theory Appl"},{"key":"5109_CR30","doi-asserted-by":"crossref","unstructured":"Veneris AG, Chang R, Abadir MS, Amiri M (2004) Fault equivalence and diagnostic test generation using atpg. In: Proceedings IEEE international symposium on circuits and systems, 2004, pp 221\u2013224","DOI":"10.1109\/ISCAS.2004.1329502"},{"issue":"4","key":"5109_CR31","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1109\/54.32421","volume":"6","author":"JA Waicukauski","year":"1989","unstructured":"Waicukauski JA, Lindbloom E (1989) Failure diagnosis of structured VLSI. IEEE Des Test Comput 6(4):49\u201360","journal-title":"IEEE Des Test Comput"},{"key":"5109_CR32","unstructured":"Wunderlich H-J (2005) From embedded test to embedded diagnosis. In: Proceedings European test symposium, Tallin, pp 216\u2013221"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-009-5109-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-009-5109-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-009-5109-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,31]],"date-time":"2019-05-31T01:57:44Z","timestamp":1559267864000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-009-5109-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7,29]]},"references-count":32,"journal-issue":{"issue":"4-5","published-print":{"date-parts":[[2009,8]]}},"alternative-id":["5109"],"URL":"https:\/\/doi.org\/10.1007\/s10836-009-5109-3","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,7,29]]}}}