{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:02:38Z","timestamp":1725548558431},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2009,10,8]],"date-time":"2009-10-08T00:00:00Z","timestamp":1254960000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2009,12]]},"DOI":"10.1007\/s10836-009-5115-5","type":"journal-article","created":{"date-parts":[[2009,10,7]],"date-time":"2009-10-07T06:54:17Z","timestamp":1254898457000},"page":"323-335","source":"Crossref","is-referenced-by-count":7,"title":["LPTest: a Flexible Low-Power Test Pattern Generator"],"prefix":"10.1007","volume":"25","author":[{"given":"Meng-Fan","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kai-Shun","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiun-Lang","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2009,10,8]]},"reference":[{"key":"5115_CR1","doi-asserted-by":"crossref","unstructured":"Ahmed N, Tehranipoor M, Jayaram V (2007) Supply voltage noise aware ATPG for transition delay faults. In: Proc. VLSI test symposium, pp 179\u2013186","DOI":"10.1109\/VTS.2007.77"},{"issue":"3","key":"5115_CR2","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1109\/TVLSI.2004.842885","volume":"13","author":"S Bhunia","year":"2005","unstructured":"Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Trans Very Large Scale Integr Syst 13(3):384\u2013395","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5115_CR3","doi-asserted-by":"crossref","unstructured":"Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2001) A gated clock scheme for low power scan testing of logic ICs or embedded cores. In: Proc. asian test symposium, pp 253\u2013258","DOI":"10.1109\/ATS.2001.990291"},{"key":"5115_CR4","doi-asserted-by":"crossref","unstructured":"Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2002) Power driven chaining of flip-flops in scan architectures. In: Proc. international test conference, pp 796\u2013803","DOI":"10.1109\/TEST.2002.1041833"},{"key":"5115_CR5","unstructured":"Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2003) Efficient scan chain design for power minimization during scan testing under routing constraint. In: Proc. international test conference, pp 488\u2013493"},{"key":"5115_CR6","doi-asserted-by":"crossref","unstructured":"Butler KM, Saxena J, Fryars T, Hetherington G, Jain A, Lewis J (2004) Minimizing power consumption in scan testing: pattern generation and DFT techniques. In: Proc. international test conference, pp 355\u2013364","DOI":"10.1109\/TEST.2004.1386971"},{"key":"5115_CR7","doi-asserted-by":"crossref","unstructured":"Corno F, Prinetto P, Redaudengo M, Reorda M (1998) Test pattern generation methodology for low power consumption. In: Proc. VLSI test symposium, pp 453\u2013457","DOI":"10.1109\/VTEST.1998.670912"},{"key":"5115_CR8","doi-asserted-by":"crossref","unstructured":"Devanathan V, Ravikumar C, Kamakoti V (2007) Glitch-aware pattern generation and optimization framework for power-safe scan test. In: Proc. VLSI test symposium, pp 167\u2013172","DOI":"10.1109\/VTS.2007.34"},{"key":"5115_CR9","doi-asserted-by":"crossref","unstructured":"Gerstendorfer S, Wunderlich H-J (1999) Minimized power consumption for scan-based BIST. In: Proc. international test conference, pp 77\u201384","DOI":"10.1109\/TEST.1999.805616"},{"issue":"3","key":"5115_CR10","first-page":"676","volume":"30","author":"P Goel","year":"1981","unstructured":"Goel P (1981) An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Comput 30(3):676\u2013683","journal-title":"IEEE Trans Comput"},{"key":"5115_CR11","unstructured":"Huang X-L, Huang J-L (2006) A routability constrained scan chain ordering technique for test power reduction. In: Proc. Asia and South Pacific design automation conference, pp 648\u2013652"},{"key":"5115_CR12","doi-asserted-by":"crossref","unstructured":"Kajihara S, Ishida K, Miyase K (2002) Test vector modification for power reduction during scan testing. In: Proc. VLSI test symposium, pp 160\u2013165","DOI":"10.1109\/VTS.2002.1011128"},{"key":"5115_CR13","doi-asserted-by":"crossref","unstructured":"Li W, Reddy SM, Pomeranz I (2005) On reducing peak current and power during test. In: Proc. computer society annual symposium on VLSI, pp 156\u2013161","DOI":"10.1109\/ISVLSI.2005.53"},{"issue":"2","key":"5115_CR14","doi-asserted-by":"crossref","first-page":"321","DOI":"10.1109\/TCAD.2003.822103","volume":"23","author":"K Miyase","year":"2004","unstructured":"Miyase K, Kajihara S (2004) XID: don\u2019t care identification of test patterns for combinational circuits. IEEE Trans Comput-Aided Des 23(2):321\u2013326","journal-title":"IEEE Trans Comput-Aided Des"},{"key":"5115_CR15","doi-asserted-by":"crossref","unstructured":"Pouya B, Crouch A (2000) Optimization trade-offs for vector volume and test power. In: Proc. international test conference, pp 873\u2013881","DOI":"10.1109\/TEST.2000.894298"},{"key":"5115_CR16","unstructured":"Ravi S (2007) Power-aware test: challenges and solutions. In: Proc. international test conference"},{"key":"5115_CR17","doi-asserted-by":"crossref","unstructured":"Remersaro S, Lin X, Reddy SM, Pomeranz I, Rajski J (2007) Low shift and capture power scan tests. In: Proc. international conference on VLSI design, pp 793\u2013798","DOI":"10.1109\/VLSID.2007.101"},{"key":"5115_CR18","doi-asserted-by":"crossref","unstructured":"Remersaro S, Lin X, Zhang Z, Reddy SM, Pomeranz I, Rajski J (2006) Preferred fill: a scalable method to reduce capture power for scan based designs. In: Proc. international test conference, pp 32.2.1\u201332.2.10","DOI":"10.1109\/TEST.2006.297694"},{"issue":"7","key":"5115_CR19","doi-asserted-by":"crossref","first-page":"1142","DOI":"10.1109\/TCAD.2004.829797","volume":"23","author":"P Rosinger","year":"2004","unstructured":"Rosinger P, Al-Hashimi BM, Nicolici N (2004) Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans Comput-Aided Des 23(7):1142\u20131153","journal-title":"IEEE Trans Comput-Aided Des"},{"key":"5115_CR20","doi-asserted-by":"crossref","unstructured":"Sankaralingam R, Touba N (2002) Controlling peak power during scan testing. In Proc. VLSI test symposium, pp 153\u2013159","DOI":"10.1109\/VTS.2002.1011127"},{"key":"5115_CR21","doi-asserted-by":"crossref","unstructured":"Sankaralingam R, Oruganti R, Touba N (2000) Static compaction techniques to control scan vector power dissipation. In: Proc. VLSI test symposium, pp 35\u201340","DOI":"10.1109\/VTEST.2000.843824"},{"key":"5115_CR22","doi-asserted-by":"crossref","unstructured":"Sankaralingam R, Pouya B, Touba N (2001) Reducing power dissipation during test using scan chain disable. In: Proc. VLSI test symposium, pp 319\u2013324","DOI":"10.1109\/VTS.2001.923456"},{"key":"5115_CR23","doi-asserted-by":"crossref","unstructured":"Saxena J, Butler KM, Whetsel L (2001) An analysis of power reduction techniques in scan testing. In: Proc. international test conference, pp 670\u2013677","DOI":"10.1109\/TEST.2001.966687"},{"key":"5115_CR24","doi-asserted-by":"crossref","unstructured":"Saxena J, Butler KM, Jayaram VB, Kundu S, Arvind NV, Sreeprakash P, Hachinger M (2003) A case study of IR-drop in structured at-speed testing. In: Proc. international test conference, pp 1098\u20131104","DOI":"10.1109\/TEST.2003.1271098"},{"key":"5115_CR25","doi-asserted-by":"crossref","unstructured":"Sharifi S, Jaffari J, Hosseinabady M, Afzali-Kusha A, Navabi Z (2005) Simultaneous reduction of dynamic and static power in scan structures. In: Proc. design, automation and test in Europe, pp 846\u2013851","DOI":"10.1109\/DATE.2005.270"},{"key":"5115_CR26","doi-asserted-by":"crossref","unstructured":"Sinanoglu O, Orailoglu A (2004) Scan power minimization through stimulus and response transformations. In: Proc. design, automation and test in Europe, pp 404\u2013409","DOI":"10.1109\/DATE.2004.1268880"},{"issue":"8","key":"5115_CR27","doi-asserted-by":"crossref","first-page":"954","DOI":"10.1109\/TCAD.2002.800460","volume":"21","author":"S Wang","year":"2002","unstructured":"Wang S, Gupta SK (2002) An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Trans Comput-Aided Des 21(8):954\u2013968","journal-title":"IEEE Trans Comput-Aided Des"},{"issue":"8","key":"5115_CR28","doi-asserted-by":"crossref","first-page":"1565","DOI":"10.1109\/TCAD.2005.855927","volume":"25","author":"S Wang","year":"2006","unstructured":"Wang S, Gupta SK (2006) LT-RTPG: a new test-per-scan BIST TPG for low switching activity. IEEE Trans Comput-Aided Des 25(8):1565\u20131574","journal-title":"IEEE Trans Comput-Aided Des"},{"key":"5115_CR29","unstructured":"Wen X, Yamashita Y, Kajihara S, Wang L-T, Saluja KK, Kinoshita K (2005) On low-capture-power test generation for scan testing. In: Proc. VLSI test symposium, pp 265\u2013270"},{"key":"5115_CR30","unstructured":"Wen X, Yamashita Y, Morishima S, Kajihara S, Wang L-T, Saluja KK, Kinoshita K (2005) Low-capture-power test generation for scan-based at-speed testing. In: Proc. international test conference, pp 1019\u20131028"},{"key":"5115_CR31","unstructured":"Wen X, Kajihara S, Miyase K, Suzuki T, Saluja KK, Wang L-T, Abdel-Hafez KS, Kinoshita K (2006) A new ATPG method for efficient capture power reduction during scan testing. In: Proc. VLSI test symposium, pp 58\u201365"},{"key":"5115_CR32","unstructured":"Wen X, Miyase K, Kajihara S, Suzuki T, Yamato Y, Girard P, Ohsumi Y, Wang L-T (2007) A novel scheme to reduce power supply noise for high-quality at-speed scan testing. In: Proc. international test conference, pp 25.1.1\u201325.1.10"},{"key":"5115_CR33","doi-asserted-by":"crossref","unstructured":"Whetsel L (2000) Adapting scan architectures for low power operation. In: Proc. international test conference, pp 863\u2013872","DOI":"10.1109\/TEST.2000.894297"},{"key":"5115_CR34","doi-asserted-by":"crossref","unstructured":"Wohl P, Waicukauski JA, Patel S, Amin MB (2003) Efficient compression and application of deterministic patterns in a logic bist architecture. In: Proc. design automation conference, pp 566\u2013569","DOI":"10.1145\/775832.775976"},{"key":"5115_CR35","doi-asserted-by":"crossref","unstructured":"Wu M-F, Hu K-S, Huang J-L (2007) An efficient peak power reduction technique for scan testing. In: Proc. Asian test symposium, pp 111\u2013114","DOI":"10.1109\/ATS.2007.54"},{"key":"5115_CR36","doi-asserted-by":"crossref","unstructured":"Yoshida T, Watari M (2002) MD-scan method for low power scan testing. In: Proc. Asian test symposium, pp 80\u201385","DOI":"10.1109\/ATS.2002.1181690"},{"key":"5115_CR37","doi-asserted-by":"crossref","unstructured":"Yoshida T, Watari M (2003) A new approach for low power scan testing. In: Proc. international test conference, pp 480\u2013487","DOI":"10.1109\/TEST.2003.1270873"},{"key":"5115_CR38","doi-asserted-by":"crossref","unstructured":"Zorian Y (1993) A distributed BIST control scheme for complex VLSI devices. In: Proc. VLSI test symposium, pp 4\u20139","DOI":"10.1109\/VTEST.1993.313316"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-009-5115-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-009-5115-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-009-5115-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T21:57:44Z","timestamp":1559253464000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-009-5115-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,10,8]]},"references-count":38,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2009,12]]}},"alternative-id":["5115"],"URL":"https:\/\/doi.org\/10.1007\/s10836-009-5115-5","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,10,8]]}}}