{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T18:27:53Z","timestamp":1649183273315},"reference-count":52,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2010,6,4]],"date-time":"2010-06-04T00:00:00Z","timestamp":1275609600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2010,8]]},"DOI":"10.1007\/s10836-010-5159-6","type":"journal-article","created":{"date-parts":[[2010,6,3]],"date-time":"2010-06-03T09:48:55Z","timestamp":1275558535000},"page":"465-481","source":"Crossref","is-referenced-by-count":4,"title":["On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power"],"prefix":"10.1007","volume":"26","author":[{"given":"Sobeeh","family":"Almukhaizim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shouq","family":"Alsubaihi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2010,6,4]]},"reference":[{"key":"5159_CR1","doi-asserted-by":"crossref","unstructured":"Ahmed N, Ravikumar CP, Tehranipoor M, Plusquellic J (2005) At-speed transition fault testing with low speed scan enable. In: VLSI test symposium, pp 42\u201347","DOI":"10.1109\/VTS.2005.31"},{"key":"5159_CR2","doi-asserted-by":"crossref","unstructured":"Almukhaizim S, Sinanoglu O (2008) Peak power reduction through dynamic partitioning of scan chains. In: International test conference, p 9.2","DOI":"10.1109\/TEST.2008.4700573"},{"issue":"2","key":"5159_CR3","doi-asserted-by":"crossref","first-page":"298","DOI":"10.1109\/TCAD.2008.2009159","volume":"28","author":"S Almukhaizim","year":"2009","unstructured":"Almukhaizim S, Sinanoglu O (2009) Dynamic scan chain partitioning for reducing peak shift power during test. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(2):298\u2013302","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"issue":"8","key":"5159_CR4","doi-asserted-by":"crossref","first-page":"1547","DOI":"10.1109\/TCAD.2005.855933","volume":"25","author":"S Almukhaizim","year":"2006","unstructured":"Almukhaizim S, Drineas P, Makris Y (2006) Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines. IEEE Trans Comput-Aided Des Integr Circuits Syst 25(8):1547\u20131554","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"issue":"3","key":"5159_CR5","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1109\/TVLSI.2004.842885","volume":"13","author":"S Bhunia","year":"2005","unstructured":"Bhunia S, Mahmoodi-Meimand H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(3):384\u2013395","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"5159_CR6","doi-asserted-by":"crossref","unstructured":"Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2001) A gated clock scheme for low power scan testing of logic ICs or embedded cores. In: Asian test symposium, pp 253\u2013258","DOI":"10.1109\/ATS.2001.990291"},{"key":"5159_CR7","doi-asserted-by":"crossref","unstructured":"Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S, Virazel A (2004) Design of routing-constrained low power scan chains. In: Design, automation and test in Europe conference, pp 62\u201367","DOI":"10.1109\/DATE.2004.1268828"},{"key":"5159_CR8","doi-asserted-by":"crossref","unstructured":"Butler KM, Saxena J, Fryars T, Hetherington G (2004) Minimizing power consumption in scan testing: pattern generation and DFT techniques. In: International test conference, pp 355\u2013364","DOI":"10.1109\/TEST.2004.1386971"},{"key":"5159_CR9","unstructured":"Chiu M-H, Li JC-M (2005) Jump scan: a DFT technique for low power testing. In: VLSI test symposium, pp 277\u2013282"},{"issue":"12","key":"5159_CR10","doi-asserted-by":"crossref","first-page":"1325","DOI":"10.1109\/43.736572","volume":"17","author":"V Dabholkar","year":"1998","unstructured":"Dabholkar V, Chakravarty S, Pomeranz I, Reddy SM (1998) Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans Comput-Aided Des Integr Circuits Syst 17(12):1325\u20131333","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5159_CR11","doi-asserted-by":"crossref","unstructured":"Furukawa H, Wen X, Wang L-T, Sheu B, Jiang Z, Wu S (2006) A novel and practical control scheme for inter-clock at-speed testing. In: International test conference, pp 17.2.1\u201317.2.10","DOI":"10.1109\/TEST.2006.297641"},{"key":"5159_CR12","doi-asserted-by":"crossref","unstructured":"Gerstend\u00f6rfer S, Wunderlich H-J (1999) Minimized power consumption for scan-based BIST. In: International test conference, pp 77\u201384","DOI":"10.1109\/TEST.1999.805616"},{"issue":"3","key":"5159_CR13","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1109\/MDT.2002.1003802","volume":"19","author":"P Girard","year":"2002","unstructured":"Girard P (2002) Survey of low-power testing of VLSI circuits. IEEE Des Test 19(3):82\u201392","journal-title":"IEEE Des Test"},{"key":"5159_CR14","doi-asserted-by":"crossref","unstructured":"Girard P, Guiller L, Landrault C, Pravossoudovitch S (1999) Circuit partitioning for low power BIST design with minimized peak power consumption. In: Asian test symposium, pp 89\u201394","DOI":"10.1109\/ATS.1999.810734"},{"key":"5159_CR15","doi-asserted-by":"crossref","unstructured":"Girard P, Guiller L, Landrault C, Pravossoudovitch S, Wunderlich HJ (2001) A modified clock scheme for a low power BIST test pattern generator. In: VLSI test symposium, pp 306\u2013311","DOI":"10.1109\/VTS.2001.923454"},{"key":"5159_CR16","unstructured":"Huang T-C, Lee K-J (1999) An input control technique for power reduction in scan circuits during test application. In: Asian test symposium, pp 315\u2013320"},{"issue":"6","key":"5159_CR17","doi-asserted-by":"crossref","first-page":"865","DOI":"10.1287\/opre.37.6.865","volume":"37","author":"DS Johnson","year":"1989","unstructured":"Johnson DS, Aragon CR, McGeoch LA, Schevon C (1989) Optimization by simulated annealing: an experimental evaluation. Part I, graph partitioning. Oper Res 37(6):865\u2013892","journal-title":"Oper Res"},{"key":"5159_CR18","doi-asserted-by":"crossref","unstructured":"Joshi K, MacDonald E (2005) Reduction of instantaneous power by ripple scan clocking. In: VLSI test symposium, pp 271\u2013276","DOI":"10.1109\/VTS.2005.71"},{"key":"5159_CR19","doi-asserted-by":"crossref","unstructured":"Kajihara S, Ishida K, Miyase K (2002) Test vector modification for power reduction during scan testing. In: VLSI test symposium, pp 160\u2013165","DOI":"10.1109\/VTS.2002.1011128"},{"issue":"4598","key":"5159_CR20","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","volume":"220","author":"S Kirkpatrick","year":"1983","unstructured":"Kirkpatrick S, Gelatt CD, Vecchi MP (1983) Optimization by simulated annealing. Science 220(4598):671\u2013680","journal-title":"Science"},{"key":"5159_CR21","unstructured":"Lee K-J, Haung T-C, Chen J-J (2001) Peak-power reduction for multiple-scan circuits during test application. In: Asian test symposium, pp 453\u2013458"},{"issue":"5","key":"5159_CR22","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1109\/MDT.2003.1232252","volume":"20","author":"X Lin","year":"2003","unstructured":"Lin X, Press R, Rajski J, Reuter P, Rinderknecht T, Swanson B, Tamarapalli N (2003) High-frequency, at-speed scan testing. IEEE Des Test Comput 20(5):17\u201325","journal-title":"IEEE Des Test Comput"},{"issue":"3","key":"5159_CR23","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1109\/MDT.2004.17","volume":"21","author":"TM Mak","year":"2004","unstructured":"Mak TM, Krstic A, Cheng K-T, Wang L-C (2004) New challenges in delay testing of nanometer, multigigahertz designs. IEEE Des Test Comput 21(3):241\u2013247","journal-title":"IEEE Des Test Comput"},{"key":"5159_CR24","doi-asserted-by":"crossref","unstructured":"Maxwell PC, Aitken RC, Kollitz KR, Brown AC (1996) IDDQ and AC scan: the war against unmodelled defects. International test conference, pp 250\u2013258","DOI":"10.1109\/TEST.1996.556969"},{"issue":"6","key":"5159_CR25","doi-asserted-by":"crossref","first-page":"1087","DOI":"10.1063\/1.1699114","volume":"21","author":"N Metropolis","year":"1953","unstructured":"Metropolis N, Rosenbluth A, Rosenbluth M, Teller A, Teller E (1953) Equation of state calculation by fast computing machines. J Chem Phys 21(6):1087\u20131092","journal-title":"J Chem Phys"},{"key":"5159_CR26","doi-asserted-by":"crossref","unstructured":"Nicolici N, Al-Hashimi BM, Williams AC (2000) Minimisation of power dissipation during test application in full scan sequential circuits using primary input freezing. In: IET computers and digital techniques, pp 313\u2013322","DOI":"10.1049\/ip-cdt:20000537"},{"key":"5159_CR27","doi-asserted-by":"crossref","unstructured":"Nigh P, Needham W, Butler K, Maxwell P, Aitken R (1997) An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. In: VLSI test symposium, pp 459\u2013464","DOI":"10.1109\/VTEST.1997.600334"},{"key":"5159_CR28","doi-asserted-by":"crossref","unstructured":"Park I, McCluskey EJ (2008) Launch-on-shift-capture transition tests. In: International test conference, p 35.3","DOI":"10.1109\/TEST.2008.4700648"},{"key":"5159_CR29","doi-asserted-by":"crossref","unstructured":"Pouya B, Crouch AL (2000) Optimization trade-offs for vector volume and test power. In: International test conference, pp 873\u2013881","DOI":"10.1109\/TEST.2000.894298"},{"issue":"4","key":"5159_CR30","doi-asserted-by":"crossref","first-page":"365","DOI":"10.1007\/BF02579324","volume":"7","author":"P Raghavan","year":"1987","unstructured":"Raghavan P, Thompson C (1987) Randomized rounding: a technique for provably good algorithms and algorithmic proofs. Combinatorica 7(4):365\u2013374","journal-title":"Combinatorica"},{"key":"5159_CR31","doi-asserted-by":"crossref","unstructured":"Remersaro S, Lin X, Zhang Z, Reddy SM, Pomeranz I, Rajski J (2006) Preferred fill: a scalable method to reduce capture power for scan based designs. In: International test conference, p 32.2","DOI":"10.1109\/TEST.2006.297694"},{"issue":"7","key":"5159_CR32","doi-asserted-by":"crossref","first-page":"1142","DOI":"10.1109\/TCAD.2004.829797","volume":"23","author":"PM Rosinger","year":"2004","unstructured":"Rosinger PM, Al-Hashimi BM, Nicolici N (2004) Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans Comput-Aided Des Integr Circuits Syst 23(7):1142\u20131153","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5159_CR33","doi-asserted-by":"crossref","unstructured":"Sankaralingam R, Touba NA (2002) Inserting test points to control peak power during scan testing. In: International symposium on defect and fault-tolerance in VLSI systems, pp 138\u2013146","DOI":"10.1109\/DFTVS.2002.1173510"},{"key":"5159_CR34","doi-asserted-by":"crossref","unstructured":"Sankaralingam R, Touba NA (2002) Controlling peak power during scan testing. In: VLSI test symposium, pp 153\u2013159","DOI":"10.1109\/VTS.2002.1011127"},{"key":"5159_CR35","doi-asserted-by":"crossref","unstructured":"Sankaralingam R, Touba NA, Pouya B (2001) Reducing power dissipation during test using scan chain disable. In: VLSI test symposium, pp 319\u2013324","DOI":"10.1109\/VTS.2001.923456"},{"issue":"3","key":"5159_CR36","doi-asserted-by":"crossref","first-page":"368","DOI":"10.1109\/92.311647","volume":"2","author":"J Savir","year":"1994","unstructured":"Savir J, Patil S (1994) On broad-side delay test. IEEE Trans Very Large Scale Integr (VLSI) Syst 2(3):368\u2013372","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"5159_CR37","doi-asserted-by":"crossref","unstructured":"Saxena J, Butler KM, Jayaram VB, Kundu S, Arvind NV, Sreeprakash P, Hachinger M (2003) A case study of IR-drop in structured at-speed testing. In: International test conference, pp 1098\u20131104","DOI":"10.1109\/TEST.2003.1271098"},{"key":"5159_CR38","doi-asserted-by":"crossref","unstructured":"Saxena J, Butler KM, Gatt J, Raghuraman R, Kumar SP, Basu S, Campbell DJ, Berech, J (2002) Scan-based transition fault testing\u2014implementation and low cost test challenges. In: International test conference, pp 1120\u20131129","DOI":"10.1109\/TEST.2002.1041869"},{"key":"5159_CR39","doi-asserted-by":"crossref","unstructured":"Sharifi S, Jaffari J, Hosseinabady M, Afzali-Kusha A, Navabi Z (2005) Simultaneous reduction of dynamic and static power in scan structures. In: Design, automation and test in Europe conference, pp 846\u2013851","DOI":"10.1109\/DATE.2005.270"},{"key":"5159_CR40","doi-asserted-by":"crossref","unstructured":"Sinanoglu O, Orailoglu A (2003) Modeling scan chain modifications for scan-in test power minimization. In: International test conference, pp 602\u2013611","DOI":"10.1109\/TEST.2003.1270887"},{"issue":"2","key":"5159_CR41","doi-asserted-by":"crossref","first-page":"215","DOI":"10.1109\/TR.2005.847276","volume":"54","author":"O Sinanoglu","year":"2005","unstructured":"Sinanoglu O, Orailoglu A (2005) Test power reductions through computationally efficient, decoupled scan chain modifications. IEEE Trans Reliab 54(2):215\u2013223","journal-title":"IEEE Trans Reliab"},{"key":"5159_CR42","doi-asserted-by":"crossref","unstructured":"Sinanoglu O, Bayraktaroglu I, Orailoglu A (2002) Test power reduction through minimization of scan chain transitions. In: VLSI test symosium, pp 166\u2013171","DOI":"10.1109\/VTS.2002.1011129"},{"key":"5159_CR43","doi-asserted-by":"crossref","unstructured":"Sinanoglu O, Bayraktaroglu I, Orailoglu A (2002) Scan power reduction through test data transition frequency analysis. In: International test conference, pp 844\u2013850","DOI":"10.1109\/TEST.2002.1041838"},{"issue":"4","key":"5159_CR44","doi-asserted-by":"crossref","first-page":"457","DOI":"10.1023\/A:1024600311740","volume":"19","author":"O Sinanoglu","year":"2003","unstructured":"Sinanoglu O, Bayraktaroglu I, Orailoglu A (2003) Reducing average and peak test power through scan chain modification. J Electron Test 19(4):457\u2013467","journal-title":"J Electron Test"},{"key":"5159_CR45","unstructured":"Smith GL (1985) Model for delay faults based upon paths. In: International test conference, pp 342\u2013351"},{"key":"5159_CR46","unstructured":"Waicukauski JA, Lindbloom E, Iyengar VS, Rosen BK (1986) Transition fault simulation by parallel pattern single fault propagation. In: International test conference, pp 542\u2013551"},{"key":"5159_CR47","unstructured":"Wen X, Yamashita Y, Kajihara S, Wang L-T, Saluja KK, Kinoshita K (2005) On low-capture-power test generation for scan testing. In: VLSI test symposium, pp 265\u2013270"},{"key":"5159_CR48","unstructured":"Wen X, Yamashita Y, Morishima S, Kajihara S, Wang L-T, Saluja KW, Kinoshita K (2005) Low-capture-power test generation for scan-based at-speed testing. In: International test conference, pp 1019\u20131028"},{"key":"5159_CR49","unstructured":"Wen X, Kajihara S, Miyase K, Suzuki T, Saluja KW, Wang L-T, Abdel-Hafez KS, Kinoshita K (2006) A new ATPG method for efficient capture power reduction during scan testing. In: VLSI test symposium, pp 58\u201365"},{"key":"5159_CR50","doi-asserted-by":"crossref","unstructured":"Whetsel L (2000) Adapting scan architectures for low power operation. In: International test conference, pp 863\u2013872","DOI":"10.1109\/TEST.2000.894297"},{"key":"5159_CR51","doi-asserted-by":"crossref","unstructured":"Yoshida T, Watari M (2003) A new approach for low power scan testing. In: International test conference, pp 480\u2013487","DOI":"10.1109\/TEST.2003.1270873"},{"key":"5159_CR52","unstructured":"Xu G, Singh AD (2006) Low cost launch-on-shift delay test with slow scan enable. In: European test symposium, pp 9\u201314"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-010-5159-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-010-5159-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-010-5159-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,31]],"date-time":"2019-05-31T01:57:45Z","timestamp":1559267865000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-010-5159-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6,4]]},"references-count":52,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2010,8]]}},"alternative-id":["5159"],"URL":"https:\/\/doi.org\/10.1007\/s10836-010-5159-6","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,6,4]]}}}