{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T12:15:57Z","timestamp":1780056957542,"version":"3.54.0"},"reference-count":45,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2010,8,27]],"date-time":"2010-08-27T00:00:00Z","timestamp":1282867200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2010,10]]},"DOI":"10.1007\/s10836-010-5167-6","type":"journal-article","created":{"date-parts":[[2010,8,26]],"date-time":"2010-08-26T05:46:39Z","timestamp":1282801599000},"page":"581-594","source":"Crossref","is-referenced-by-count":8,"title":["Efficient Concurrent Self-Test with Partially Specified Patterns"],"prefix":"10.1007","volume":"26","author":[{"given":"Michael A.","family":"Kochte","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Christian G.","family":"Zoellin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2010,8,27]]},"reference":[{"key":"5167_CR1","doi-asserted-by":"crossref","unstructured":"Abramovici M, Stroud CE, Hamilton C, Wijesuriya S, Verma V (1999) Using roving stars for on-line testing and diagnosis of fpgas in fault-tolerant applications. In: Proc. IEEE Int\u2019l Test Conference (ITC), pp 973\u2013982","DOI":"10.1109\/TEST.1999.805830"},{"key":"5167_CR2","unstructured":"Agarwal VK, Cerny E (1981) Store and generate built-in-testing approach. In: Proc. international symposium on Fault-Tolerant Computing (FTCS\u201881), pp 35\u201340"},{"key":"5167_CR3","doi-asserted-by":"crossref","unstructured":"Al-Asaad H, Moore P (2006) Non-concurrent on-line testing via scan chains. In: IEEE systems readiness technology conference, pp 683\u2013689","DOI":"10.1109\/AUTEST.2006.283749"},{"key":"5167_CR4","volume-title":"Built-in test for VLSI: pseudorandom techniques","author":"P Bardell","year":"1987","unstructured":"Bardell P, McAnney W, Savir J (1987) Built-in test for VLSI: pseudorandom techniques. Wiley-Interscience, New York, NY, USA"},{"issue":"3","key":"5167_CR5","doi-asserted-by":"crossref","first-page":"258","DOI":"10.1109\/MDT.2005.69","volume":"22","author":"R Baumann","year":"2005","unstructured":"Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3):258\u2013266","journal-title":"IEEE Des Test Comput"},{"key":"5167_CR6","doi-asserted-by":"crossref","unstructured":"Borkar S, Karnik T, De V (2004) Design and reliability challenges in nanometer technologies. In: Proc. ACM\/IEEE Design Automation Conference (DAC 2004), p 75","DOI":"10.1145\/996566.996588"},{"key":"5167_CR7","doi-asserted-by":"crossref","unstructured":"Boul\u00e9 M, Zilic Z (2008) Generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring. Springer","DOI":"10.1007\/978-1-4020-8586-4"},{"key":"5167_CR8","doi-asserted-by":"crossref","unstructured":"Drineas P, Makris Y (2003) Concurrent fault detection in random combinational logic. In: Int\u2019l Symposium on Quality of Electronic Design (ISQED), pp 425\u2013430","DOI":"10.1109\/ISQED.2003.1194770"},{"issue":"6","key":"5167_CR9","doi-asserted-by":"crossref","first-page":"1729","DOI":"10.1109\/TIM.2003.818733","volume":"52","author":"P Drineas","year":"2003","unstructured":"Drineas P, Makris Y (2003) SPaRe: selective partial replication for concurrent fault-detection in FSMs. IEEE Trans Instrum Meas 52(6):1729\u20131737","journal-title":"IEEE Trans Instrum Meas"},{"key":"5167_CR10","doi-asserted-by":"crossref","unstructured":"El-Maleh A, Al-Suwaiyan A (2002) An efficient test relaxation technique for combinational & full-scan sequential circuits. In: Proc. IEEE VLSI test symposium, pp 53\u201359","DOI":"10.1109\/VTS.2002.1011111"},{"key":"5167_CR11","doi-asserted-by":"crossref","unstructured":"Gherman V, Wunderlich H-J, Mascarenhas RD, Schl\u00f6ffel J, Garbers M (2007) Synthesis of irregular combinational functions with large don\u2019t care sets. In: Proc. ACM great lakes symposium on VLSI, pp 287\u2013292","DOI":"10.1145\/1228784.1228856"},{"issue":"12","key":"5167_CR12","doi-asserted-by":"crossref","first-page":"1446","DOI":"10.1109\/TCAD.2002.804387","volume":"21","author":"E Gizdarski","year":"2002","unstructured":"Gizdarski E, Fujiwara H (2002) Spirit: a highly robust combinational test generation algorithm. IEEE Trans Computer-Aided Design Integr Circuits Syst 21(12):1446\u20131458","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"key":"5167_CR13","unstructured":"Hellebrand S, Tarnick S, Courtois B, Rajski J (1992) Generation of vector patterns through reseeding of multipe-polynominal linear feedback shift registers. In: Proc. IEEE Int\u2019l Test Conference (ITC), pp 120\u2013129"},{"key":"5167_CR14","doi-asserted-by":"crossref","unstructured":"Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J (1995) Pattern generation for a deterministic BIST scheme. In: Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp 88\u201394","DOI":"10.1109\/ICCAD.1995.479997"},{"key":"5167_CR15","doi-asserted-by":"crossref","unstructured":"Inoue H, Li Y, Mitra S (2008) VAST: virtualization-assisted concurrent autonomous self-test. In: Proc. IEEE Int\u2019l Test Conference (ITC), p 12.3","DOI":"10.1109\/TEST.2008.4700583"},{"issue":"12","key":"5167_CR16","doi-asserted-by":"crossref","first-page":"1496","DOI":"10.1109\/43.476580","volume":"14","author":"S Kajihara","year":"1995","unstructured":"Kajihara S, Pomeranz I, Kinoshita K, Reddy SM (1995) Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans Computer-Aided Design Integr Circuits Syst 14(12):1496\u20131504","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"key":"5167_CR17","doi-asserted-by":"crossref","unstructured":"Karkala M, Touba NA, Wunderlich H-J (1998) Special ATPG to correlate test patterns for low-overhead mixed-mode BIST. In: Proceedings of the 7th Asian Test Symposium (ATS \u201898), pp 492\u2013499","DOI":"10.1109\/ATS.1998.741662"},{"key":"5167_CR18","doi-asserted-by":"crossref","unstructured":"Kochte MA, Zoellin CG, Imhof ME, Wunderlich HJ (2008) Test set stripping limiting the maximum number of specified bits. In: Proc. IEEE int\u2019l symposium on electronic design, test and applications (DELTA), pp 581\u2013586","DOI":"10.1109\/DELTA.2008.64"},{"key":"5167_CR19","doi-asserted-by":"crossref","unstructured":"Kochte M, Zoellin C, Wunderlich H (2009) Concurrent self-test with partially specified patterns for low test latency and overhead. In: IEEE European test symposium, pp 53\u201358","DOI":"10.1109\/ETS.2009.26"},{"key":"5167_CR20","doi-asserted-by":"crossref","unstructured":"Koren I, Krishna C (2007) Fault-tolerant systems. Morgan Kaufmann","DOI":"10.1016\/B978-012088525-1\/50007-9"},{"key":"5167_CR21","unstructured":"Lala P (2001) Self-checking and fault-tolerant digital design. Morgan Kaufmann"},{"issue":"4","key":"5167_CR22","doi-asserted-by":"crossref","first-page":"419","DOI":"10.1109\/12.54835","volume":"39","author":"R Leveugle","year":"1990","unstructured":"Leveugle R, Saucier G (1990) Optimized synthesis of concurrently checked controllers. IEEE Trans Comput 39(4):419\u2013425","journal-title":"IEEE Trans Comput"},{"key":"5167_CR23","doi-asserted-by":"crossref","unstructured":"Mitra S, McCluskey EJ (2000) Which concurrent error detection scheme to choose? In: Proc. IEEE Int\u2019l Test Conference (ITC), pp 985\u2013994","DOI":"10.1109\/TEST.2000.894311"},{"issue":"2","key":"5167_CR24","doi-asserted-by":"crossref","first-page":"321","DOI":"10.1109\/TCAD.2003.822103","volume":"23","author":"K Miyase","year":"2004","unstructured":"Miyase K, Kajihara S (2004) XID: Don\u2019t care identification of test patterns for combinational circuits. IEEE Trans Computer-Aided Design Integr Circuits Syst 23(2):321\u2013326","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"key":"5167_CR25","doi-asserted-by":"crossref","unstructured":"Mohanram K, Sogomonyan ES, G\u00f6ssel M, Touba NA (2003) Synthesis of low-cost parity-based partially self-checking circuits. In: Proc. IEEE Int\u2019l On-line Testing Symposium (IOLTS), pp 35\u201340","DOI":"10.1109\/OLT.2003.1214364"},{"key":"5167_CR26","doi-asserted-by":"crossref","unstructured":"Nassif SR (2001) Modeling and analysis of manufacturing variations. In: Proc. IEEE custom integrated circuits conference, pp 223\u2013228","DOI":"10.1109\/CICC.2001.929760"},{"issue":"1","key":"5167_CR27","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1023\/A:1008244815697","volume":"12","author":"M Nicolaidis","year":"1998","unstructured":"Nicolaidis M, Zorian Y (1998) On-line testing for VLSI: a compendium of approaches. J Electron Test 12(1):7\u201320","journal-title":"J Electron Test"},{"issue":"1","key":"5167_CR28","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1049\/ip-cdt:20050129","volume":"153","author":"I Pomeranz","year":"2006","unstructured":"Pomeranz I, Reddy S (2006) Reducing the number of specified values per test vector by increasing the test set size. IEE Proc Comput Digit Tech 153(1):39\u201346","journal-title":"IEE Proc Comput Digit Tech"},{"key":"5167_CR29","unstructured":"Pradhan D (1996) Fault-tolerant computer design. Prentice Hall"},{"key":"5167_CR30","unstructured":"Saluja K, Sharma R, Kime C (1987) Concurrent comparative testing using BIST resources. In: Proc. IEEE Int\u2019l Conference on Computer-Aided Design (ICCAD), pp 336\u2013337"},{"issue":"12","key":"5167_CR31","doi-asserted-by":"crossref","first-page":"1250","DOI":"10.1109\/43.16803","volume":"7","author":"KK Saluja","year":"1988","unstructured":"Saluja KK, Sharma R, Kime CR (1988) A concurrent testing technique for digital circuits. IEEE Trans Computer-Aided Design Integr Circuits Syst 7(12):1250\u20131260","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"issue":"4","key":"5167_CR32","doi-asserted-by":"crossref","first-page":"512","DOI":"10.1109\/TR.2003.821943","volume":"52","author":"C Scherrer","year":"2003","unstructured":"Scherrer C, Steininger A (2003) Dealing with dormant faults in an embedded fault-tolerant computer system. IEEE Trans Reliab 52(4):512\u2013522","journal-title":"IEEE Trans Reliab"},{"issue":"3","key":"5167_CR33","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1109\/TC.1987.1676899","volume":"36","author":"MA Schuette","year":"1987","unstructured":"Schuette MA, Shen JP (1987) Processor control flow monitoring using signatured instruction streams. IEEE Trans Comput 36(3):264\u2013276","journal-title":"IEEE Trans Comput"},{"key":"5167_CR34","doi-asserted-by":"crossref","unstructured":"Sharma R, Saluja K (1988) An implementation and analysis of a concurrent built-in self-test technique. In: 18th international symposium on Fault-Tolerant Computing (FTCS), pp 164\u2013169","DOI":"10.1109\/FTCS.1988.5315"},{"issue":"1","key":"5167_CR35","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1155\/1993\/34963","volume":"1","author":"R Sharma","year":"1993","unstructured":"Sharma R, Saluja KK (1993) Theory, analysis and implementation of an on-line BIST technique. VLSI Des 1(1):9\u201322","journal-title":"VLSI Des"},{"key":"5167_CR36","unstructured":"Shombert L, Siewiorek DP (1987) Using redundancy for concurrent testing and repairing of systolic arrays. In: Int\u2019l Symposium on Fault-Tolerant Computing (FTCS), pp 244\u2013249"},{"key":"5167_CR37","doi-asserted-by":"crossref","unstructured":"Steininger A, Scherrer C (1999) On the necessity of On-Line-BIST in safety-critical applications\u2014a case study. In: Proc. int\u2019l symposium on Fault-Tolerant Computing (FTCS\u201999), pp 208\u2013215","DOI":"10.1109\/FTCS.1999.781052"},{"key":"5167_CR38","unstructured":"Swaminathan S, Chakrabarty K (2001) A deterministic scan-BIST architecture with application to fieldtesting of high-availability systems. In: IEEE conference on custom integrated circuits, pp 259\u2013262"},{"key":"5167_CR39","doi-asserted-by":"crossref","unstructured":"Tafertshofer P, Ganz A, Henftling M (1997) A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. In: Proc. Int\u2019l Conference on Computer-Aided Design (ICCAD), pp 648\u2013655","DOI":"10.1109\/ICCAD.1997.643607"},{"issue":"8","key":"5167_CR40","doi-asserted-by":"crossref","first-page":"907","DOI":"10.1109\/43.856977","volume":"19","author":"P Tafertshofer","year":"2000","unstructured":"Tafertshofer P, Ganz A, Antreich K (2000) Igraine-an implication graph-based engine for fast implication, justification, and propagation. IEEE Trans Computer-Aided Design Integr Circuits Syst 19(8):907\u2013927","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"key":"5167_CR41","unstructured":"Touba NA, McCluskey EJ (1996) Altering a pseudo-random bit sequence for scan-based BIST. In: Proc. IEEE International Test Conference (ITC), pp 167\u2013175"},{"key":"5167_CR42","doi-asserted-by":"crossref","unstructured":"Voyiatzis I, Paschalis AM, Nikolos D, Halatsis C (1998) R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. In: Proc. IEEE Int\u2019l Test Conference (ITC), pp 918\u2013925","DOI":"10.1109\/TEST.1998.743284"},{"issue":"8","key":"5167_CR43","doi-asserted-by":"crossref","first-page":"1012","DOI":"10.1109\/TC.2008.49","volume":"57","author":"I Voyiatzis","year":"2008","unstructured":"Voyiatzis I, Paschalis A, Gizopoulos D, Halatsis C, Makri F, Hatzimihail M (2008) An input vector monitoring concurrent BIST architecture based on a precomputed test set. IEEE Trans Comput 57(8):1012\u20131022","journal-title":"IEEE Trans Comput"},{"key":"5167_CR44","doi-asserted-by":"crossref","unstructured":"Wunderlich H-J, Kiefer G (1996) Bit-flipping BIST. In: Proceedings of the ACM\/IEEE International Conference on Computer-Aided Design (ICCAD \u201896), pp 337\u2013343","DOI":"10.1109\/ICCAD.1996.569803"},{"key":"5167_CR45","doi-asserted-by":"crossref","unstructured":"Zoellin C, Wunderlich H, Polian I, Becker B (2008) Selective hardening in early design steps. In: IEEE European Test Symposium (ETS), pp 185\u2013190","DOI":"10.1109\/ETS.2008.30"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-010-5167-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-010-5167-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-010-5167-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T01:36:22Z","timestamp":1740447382000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-010-5167-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,8,27]]},"references-count":45,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2010,10]]}},"alternative-id":["5167"],"URL":"https:\/\/doi.org\/10.1007\/s10836-010-5167-6","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,8,27]]}}}