{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,6,5]],"date-time":"2023-06-05T17:40:10Z","timestamp":1685986810066},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2011,3,9]],"date-time":"2011-03-09T00:00:00Z","timestamp":1299628800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1007\/s10836-011-5205-z","type":"journal-article","created":{"date-parts":[[2011,3,8]],"date-time":"2011-03-08T15:15:37Z","timestamp":1299597337000},"page":"123-136","source":"Crossref","is-referenced-by-count":12,"title":["Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems"],"prefix":"10.1007","volume":"27","author":[{"given":"Desta","family":"Tadesse","sequence":"first","affiliation":[]},{"given":"R. Iris","family":"Bahar","sequence":"additional","affiliation":[]},{"given":"Joel","family":"Grodstein","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2011,3,9]]},"reference":[{"key":"5205_CR1","doi-asserted-by":"crossref","unstructured":"Agarwal A, Dartu F, Blaauw D (2004) Statistical gate delay model considering multiple input switching. In: DAC, pp 658\u2013663","DOI":"10.1145\/996566.996746"},{"key":"5205_CR2","doi-asserted-by":"crossref","unstructured":"Aloul F, Hassoun S, Sakallah K, Blaauw D (2002) Robust sat-based search algorithm for leakage power reduction. In: PATMOS \u201902, pp 167\u2013177","DOI":"10.1007\/3-540-45716-X_17"},{"key":"5205_CR3","volume-title":"Advances in computer science, vol 58, chap. Bounded model checking","author":"A Biere","year":"2003","unstructured":"Biere A, Cimatti A, Clarke E, Strichman O, Zhu Y (2003) Advances in computer science, vol 58, chap. Bounded model checking. Academic, New York"},{"key":"5205_CR4","doi-asserted-by":"crossref","unstructured":"Biere A, Cimatti A, Clarke EM, Fujita M, Zhu Y (1999) Symbolic model checking using SAT procedures instead of BDDs. In: ACM\/IEEE conference on design automation, pp 317\u2013320","DOI":"10.1145\/309847.309942"},{"key":"5205_CR5","unstructured":"Blaauw D, Zolotov V, Sundareswaran S, Oh C, Panda R (2000) Slope propagation in static timing analysis. In: ICCAD"},{"key":"5205_CR6","unstructured":"Chen P, Keutzer K (1999) Towards true crosstalk noise analysis. In: ICCAD, pp 132\u2013138"},{"key":"5205_CR7","unstructured":"Chen P, Kirkpatrick D, Keutzer K (2000) Switching window computation for static timing analysis in presence of crosstalk noise. In: ICCAD, pp 331\u2013337"},{"issue":"12","key":"5205_CR8","doi-asserted-by":"crossref","first-page":"1924","DOI":"10.1109\/43.251156","volume":"12","author":"S Devadas","year":"1993","unstructured":"Devadas S, Keutzer K, Malik S, Wang A (1993) Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans Comput-Aided Des Integr Circuits Syst 12(12):1924\u20131936","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"issue":"3","key":"5205_CR9","doi-asserted-by":"crossref","first-page":"333","DOI":"10.1109\/92.311642","volume":"2","author":"S Devadas","year":"1994","unstructured":"Devadas S, Keutzer K, Malik S, Wang A (1994) Certified timing verification and the transition delay of a logic circuit. IEEE Trans VLSI Syst 2(3):333\u2013342","journal-title":"IEEE Trans VLSI Syst"},{"key":"5205_CR10","doi-asserted-by":"crossref","unstructured":"Josephson D (2002) The manic depression of microprocessor debug. In: Test conference, 2002. Proceedings. International, pp 657\u2013663. doi: 10.1109\/TEST.2002.1041817","DOI":"10.1109\/TEST.2002.1041817"},{"key":"5205_CR11","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5597-1","volume-title":"Delay fault testing for VLSI circuits","author":"A Krstic","year":"1998","unstructured":"Krstic A, Cheng KT (1998) Delay fault testing for VLSI circuits. Kluwer, Boston"},{"key":"5205_CR12","doi-asserted-by":"crossref","unstructured":"Krstic A, Liou J, Jiang Y, Cheng K (2001) Delay testing considering crosstalk-induced effects. In: IEEE international test conference, p 558","DOI":"10.1109\/TEST.2001.966674"},{"issue":"3","key":"5205_CR13","doi-asserted-by":"crossref","first-page":"417","DOI":"10.1109\/TCAD.2009.2013269","volume":"28","author":"YM Kuo","year":"2009","unstructured":"Kuo YM, Chang YL, Chang S (2009) Efficient Boolean characteristic fuction for timed automatic test pattern generation. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(3):417\u2013425","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"issue":"1","key":"5205_CR14","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/43.108614","volume":"11","author":"T Larrabee","year":"1992","unstructured":"Larrabee T (1992) Test pattern generation using boolean satisfiability. IEEE Trans Comput-Aided Des Integr Circuits Syst 11(1):4\u201315","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5205_CR15","doi-asserted-by":"crossref","first-page":"360","DOI":"10.1007\/11527695_27","volume":"3542","author":"Y Mahajan","year":"2005","unstructured":"Mahajan Y, Fu Z, Malik S (2005) Zchaff2004: an efficient sat solver. Lect Notes Comput Sci 3542:360\u2013375","journal-title":"Lect Notes Comput Sci"},{"issue":"9","key":"5205_CR16","doi-asserted-by":"crossref","first-page":"1120","DOI":"10.1109\/43.159998","volume":"11","author":"P Maurer","year":"1992","unstructured":"Maurer P (1992) Two new techniques for unit-delay compiled simulation. IEEE Trans Comput-Aided Des Integr Circuits Syst 11(9):1120\u20131130","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5205_CR17","volume-title":"Delay models and exact timing analysis","author":"PC McGeer","year":"1997","unstructured":"McGeer PC, Saldanha A, Brayton RK, Sangiovanni-Vincentelli A (1997) Delay models and exact timing analysis. Kluwer, Norwell"},{"issue":"9","key":"5205_CR18","doi-asserted-by":"crossref","first-page":"1793","DOI":"10.1109\/TCAD.2005.859508","volume":"25","author":"A Mondal","year":"2006","unstructured":"Mondal A, Chakrabarti P (2006) Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic. IEEE Trans Comput-Aided Des Integr Circuits Syst 25(9):1793\u20131814. doi: 10.1109\/TCAD.2005.859508","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"issue":"1","key":"5205_CR19","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1109\/JSSC.2005.859894","volume":"41","author":"S Naffziger","year":"2006","unstructured":"Naffziger S, Stackhouse B, Grutkowski T, Josephson D, Desai J, Alon E, Horowitz M (2006) The implementation of a 2-core, multi-threaded itanium family processor. IEEE J Solid-State Circuits 41(1):197\u2013209. doi: 10.1109\/JSSC.2005.859894","journal-title":"IEEE J Solid-State Circuits"},{"key":"5205_CR20","doi-asserted-by":"crossref","unstructured":"Nepal K, Song H, Bahar R, Grodstein J (2004) RESTA: a robust and extendable symbolic timing analysis tool. In: GLSVLSI, pp 407\u2013412","DOI":"10.1145\/988952.989050"},{"issue":"3","key":"5205_CR21","doi-asserted-by":"crossref","first-page":"321","DOI":"10.1109\/43.594838","volume":"16","author":"A Pierzynska","year":"1997","unstructured":"Pierzynska A, Pilarski S (1997) Pitfalls in delay fault testing. IEEE Trans Comput-Aided Des Integr Circuits Syst 16(3):321\u2013329","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5205_CR22","doi-asserted-by":"crossref","unstructured":"Ran Y, Kondratyev A, Watanabe Y, Marek-Sadowska M (2004) Eliminating false positives in crosstalk noise analysis. In: IEEE\/ACM design automation and test in Europe conference, pp 1192\u20131197","DOI":"10.1109\/DATE.2004.1269054"},{"issue":"3","key":"5205_CR23","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1255456.1255473","volume":"12","author":"S Roy","year":"2007","unstructured":"Roy S, Chakrabarti PP, Dasgupta P (2007) Event propagation for accurate circuit delay calculation using sat. ACM Transact Des Automat Electron Syst 12(3):1\u201323. doi: 10.1145\/1255456.1255473","journal-title":"ACM Transact Des Automat Electron Syst"},{"key":"5205_CR24","doi-asserted-by":"crossref","unstructured":"Silva J, Sakallah K (1994) Dynamic search-space pruning techniques in path sensitization. In: DAC, pp 705\u2013711","DOI":"10.1145\/196244.196621"},{"key":"5205_CR25","unstructured":"Silva J, Sakallah K (2003) Efficient and robust test generation-based timing analysis. In: ISCAS, pp 660\u2013663"},{"issue":"1","key":"5205_CR26","doi-asserted-by":"crossref","first-page":"137","DOI":"10.1145\/504914.504920","volume":"7","author":"L Silva","year":"2002","unstructured":"Silva L, Silva J, Silveira L, Sakallah K (2002) Satisfiability models and algorithms for circuit delay computation. ACM Transact Des Automat Electron Syst (TODAES) 7(1):137\u2013158","journal-title":"ACM Transact Des Automat Electron Syst (TODAES)"},{"key":"5205_CR27","doi-asserted-by":"crossref","unstructured":"Sridharan J, Chen T (2006) Gate delay modeling with multiple input switching for static (statistical) timing analysis. In: International conference on VLSI design, p 6","DOI":"10.1109\/VLSID.2006.92"},{"key":"5205_CR28","doi-asserted-by":"crossref","unstructured":"Sun S, Du D, Chen H (1994) Efficient timing analysis for CMOS circuits considering data dependent delays. In: ICCS \u201994, pp 156\u2013159","DOI":"10.1109\/ICCD.1994.331878"},{"key":"5205_CR29","doi-asserted-by":"crossref","unstructured":"Tadesse D, Sheffield D, Leng E, Bahar RI, Grodstein J (2007) Accurate timing analysis using SAT and pattern-dependent delay models. In: IEEE\/ACM design automation and test in Europe conference, pp 1018\u20131023. Nice, France","DOI":"10.1109\/DATE.2007.364427"},{"key":"5205_CR30","doi-asserted-by":"crossref","unstructured":"Tayade R, Abraham JA (2008) Critical path selection for delay test considering coupling noise. In: IEEE European test symposium, pp 119\u2013124. Verbania, Italy","DOI":"10.1109\/ETS.2008.28"},{"key":"5205_CR31","doi-asserted-by":"crossref","first-page":"118","DOI":"10.1002\/9781118033104","volume-title":"Graphs: theory and algorithms, chap. 5","author":"K Thulasiraman","year":"1992","unstructured":"Thulasiraman K, Swamy MNS (1992) Graphs: theory and algorithms, chap. 5. Wiley, New York, p 118"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-011-5205-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-011-5205-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-011-5205-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,5]],"date-time":"2023-06-05T17:13:39Z","timestamp":1685985219000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-011-5205-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3,9]]},"references-count":31,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2011,4]]}},"alternative-id":["5205"],"URL":"https:\/\/doi.org\/10.1007\/s10836-011-5205-z","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,3,9]]}}}