{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,1,10]],"date-time":"2024-01-10T00:04:50Z","timestamp":1704845090803},"reference-count":16,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2011,5,6]],"date-time":"2011-05-06T00:00:00Z","timestamp":1304640000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2011,8]]},"DOI":"10.1007\/s10836-011-5213-z","type":"journal-article","created":{"date-parts":[[2011,5,5]],"date-time":"2011-05-05T01:46:21Z","timestamp":1304559981000},"page":"429-439","source":"Crossref","is-referenced-by-count":2,"title":["Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip"],"prefix":"10.1007","volume":"27","author":[{"given":"Kihyuk","family":"Han","sequence":"first","affiliation":[]},{"given":"Joonsung","family":"Park","sequence":"additional","affiliation":[]},{"given":"Jae Wook","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jaeyong","family":"Chung","sequence":"additional","affiliation":[]},{"given":"Eonjo","family":"Byun","sequence":"additional","affiliation":[]},{"given":"Cheol-Jong","family":"Woo","sequence":"additional","affiliation":[]},{"given":"Sejang","family":"Oh","sequence":"additional","affiliation":[]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2011,5,6]]},"reference":[{"issue":"2","key":"5213_CR1","doi-asserted-by":"crossref","first-page":"352","DOI":"10.1109\/TADVP.2004.828819","volume":"27","author":"SS Akbay","year":"2004","unstructured":"Akbay SS, Halder A, Chatterjee A, Keezer D (2004) Low-cost test of eembedded RF\/analog\/mixed-signal circuits in SOPs. IEEE Trans Adv Packaging 27(2):352\u2013363","journal-title":"IEEE Trans Adv Packaging"},{"issue":"6","key":"5213_CR2","doi-asserted-by":"crossref","first-page":"913","DOI":"10.1109\/4.585299","volume":"32","author":"CS Choy","year":"1997","unstructured":"Choy CS, Ku MH, Chan CF (1997) A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. IEEE J Solid-state Circuits 32(6):913\u2013917","journal-title":"IEEE J Solid-state Circuits"},{"issue":"2","key":"5213_CR3","doi-asserted-by":"crossref","first-page":"132","DOI":"10.1109\/6040.928747","volume":"24","author":"S Chun","year":"2001","unstructured":"Chun S, Swaminathan M, Smith LD, Srinivasan J, Jin Z, Iyer MK (2001) Modeling of simultaneous switching noise in high speed systems. IEEE Trans Adv Packaging 24(2):132\u2013142","journal-title":"IEEE Trans Adv Packaging"},{"issue":"2","key":"5213_CR4","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1109\/4.823449","volume":"35","author":"P Dudek","year":"2000","unstructured":"Dudek P, Szczepanski S, Hatfield JV (2000) A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J Solid-state Circuits 35(2):240\u2013247","journal-title":"IEEE J Solid-state Circuits"},{"issue":"6","key":"5213_CR5","doi-asserted-by":"crossref","first-page":"1286","DOI":"10.1109\/JSSC.2006.874281","volume":"41","author":"JP Jansson","year":"2006","unstructured":"Jansson JP, Manttyniemi A, Kostamovaara J (2006) A CMOS time-to-digital converter with better than 10ps single-shot precision. IEEE J Solid-state Circuits 41(6):1286\u20131296","journal-title":"IEEE J Solid-state Circuits"},{"key":"5213_CR6","doi-asserted-by":"crossref","unstructured":"Keezer DC, Minier D, Caron MC (2003) A production-oriented multiplexing system for testing above 2.5 Gbps. In: International test conference, pp 191\u2013200","DOI":"10.1109\/TEST.2003.1270840"},{"key":"5213_CR7","doi-asserted-by":"crossref","unstructured":"Keezer DC, Minier D, Caron M-C (2004) Multiplexing ATE channels for production testing at 2.5 Gbps. In: IEEE design and test of computers, pp 288\u2013301","DOI":"10.1109\/MDT.2004.37"},{"key":"5213_CR8","unstructured":"Levine PM, Roberts GW (2004) A high-resolution flash time-to-digital converter and calibration scheme. In: International test conference, pp 1148\u20131157"},{"issue":"3","key":"5213_CR9","doi-asserted-by":"crossref","first-page":"644","DOI":"10.1093\/ietele\/e90-c.3.644","volume":"E90-C","author":"JH Lim","year":"2007","unstructured":"Lim JH, HA JC, Jung WY, Kim YJ, Wee JK (2007) A novel high speed and low voltage CMOS level-up\/down shifter design for multiple-power and multiple-clock domain chips. IEICE Trans Electron E90-C(3):644\u2013648","journal-title":"IEICE Trans Electron"},{"key":"5213_CR10","doi-asserted-by":"crossref","unstructured":"Nelms M, Gorman K, Anand D (2004) Generating at-speed array fail maps with low-speed ATE. In: VLSI test symposium, pp 87\u201392","DOI":"10.1109\/VTEST.2004.1299230"},{"key":"5213_CR11","unstructured":"Restle PJ, Deutsch A (1998) Designing the best clock distribution network. In: IEEE symposium on VLSI circuits digest of technical papers, pp 2\u20135"},{"issue":"12","key":"5213_CR12","doi-asserted-by":"crossref","first-page":"1383","DOI":"10.1109\/4.262016","volume":"28","author":"R Senthinathan","year":"1993","unstructured":"Senthinathan R, Prince JL (1993) Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise. IEEE J Solid-state Circuits 28(12):1383\u20131388","journal-title":"IEEE J Solid-state Circuits"},{"key":"5213_CR13","doi-asserted-by":"crossref","unstructured":"Shimanouchi M (2004) Timing accuracy enhancement by a new calibration scheme for multi- Gbps ATE. In: International test conference, pp 567\u2013576","DOI":"10.1109\/TEST.2004.1386994"},{"key":"5213_CR14","unstructured":"Sunter S, Roy A (2007) A self-testing BOST for high-frequency PLLs, DLLs, and SerDes. In: International test conference, paper 4.3"},{"key":"5213_CR15","unstructured":"Uyttenhove K, Marques A, Steyaert M (2000) A 6-bit 1 GHz aquisition speed CMOS flash ADC with digital error correction. In: IEEE custom integrated circuit conference, pp 249\u2013252"},{"issue":"7","key":"5213_CR16","doi-asserted-by":"crossref","first-page":"1115","DOI":"10.1109\/JSSC.2003.813244","volume":"38","author":"K Uyttenhove","year":"2003","unstructured":"Uyttenhove K, Steyaert M (2003) A 1.8-V 6-bit 1.3 GHz flash ADC in 0.25- $\\upmu$ m CMOS. IEEE J Solid-state Circuits 38(7):1115\u20131122","journal-title":"IEEE J Solid-state Circuits"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-011-5213-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-011-5213-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-011-5213-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,10]],"date-time":"2019-06-10T10:19:41Z","timestamp":1560161981000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-011-5213-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5,6]]},"references-count":16,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,8]]}},"alternative-id":["5213"],"URL":"https:\/\/doi.org\/10.1007\/s10836-011-5213-z","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,5,6]]}}}