{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,12]],"date-time":"2024-08-12T12:32:19Z","timestamp":1723465939181},"reference-count":37,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2012,7,22]],"date-time":"2012-07-22T00:00:00Z","timestamp":1342915200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1007\/s10836-012-5318-z","type":"journal-article","created":{"date-parts":[[2012,8,13]],"date-time":"2012-08-13T17:04:13Z","timestamp":1344877453000},"page":"495-510","source":"Crossref","is-referenced-by-count":8,"title":["FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction"],"prefix":"10.1007","volume":"28","author":[{"given":"Nicola","family":"Bombieri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Franco","family":"Fummi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Valerio","family":"Guarnieri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2012,7,22]]},"reference":[{"key":"5318_CR1","unstructured":"Ara K, Suzuki K (2003) A proposal for transaction-level verification with component wrapper language. In: Proc. of ACM\/IEEE DATE, pp\u00a082\u201387"},{"key":"5318_CR2","unstructured":"Armstrong JR, Lam FS, Ward PC (1992) Test Generation and Fault Simulation for Behavioral Models. Prentice Hall"},{"key":"5318_CR3","doi-asserted-by":"crossref","unstructured":"Bombieri N, Fummi F, Pravadelli G (2006) On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. In: Proc. of ACM\/IEEE DATE, vol 1, pp\u00a01\u20136","DOI":"10.1109\/DATE.2006.243898"},{"key":"5318_CR4","doi-asserted-by":"crossref","unstructured":"Bombieri N, Fummi F, Pravadelli G (2007) Incremental ABV for functional validation of TL-to-RTL design refinement. In: Proc. of ACM\/IEEE DATE, pp\u00a0882\u2013887","DOI":"10.1109\/DATE.2007.364404"},{"key":"5318_CR5","doi-asserted-by":"crossref","unstructured":"Bombieri N, Fummi F, Pravadelli G, Marques-Silva J (2007) Towards equivalence checking between TLM and RTL models. In: Proc. of ACM\/IEEE MEMOCODE, pp\u00a0113\u2013122","DOI":"10.1109\/MEMCOD.2007.371236"},{"key":"5318_CR6","doi-asserted-by":"crossref","unstructured":"Bombieri N, Fummi F, Pravadelli G, Hampton M, Letombe F (2009) Functional qualification of TLM verification. In: Proc. of ACM\/IEEE DATE, pp\u00a0190\u2013195","DOI":"10.1109\/DATE.2009.5090656"},{"key":"5318_CR7","doi-asserted-by":"crossref","unstructured":"Bombieri N, Fummi F, Guarnieri V (2011) Accelerating RTL fault simulation through RTL-to-TLM abstraction. In: Proc. of IEEE ETS, pp\u00a0117\u2013122","DOI":"10.1109\/ETS.2011.58"},{"issue":"12","key":"5318_CR8","doi-asserted-by":"crossref","first-page":"1730","DOI":"10.1109\/TC.2010.187","volume":"60","author":"N Bombieri","year":"2011","unstructured":"Bombieri N, Fummi F, Pravadelli G (2011) Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions. IEEE Trans Comput 60(12):1730\u20131743","journal-title":"IEEE Trans Comput"},{"key":"5318_CR9","doi-asserted-by":"crossref","unstructured":"Borgatti M, Capello A, Rossi U, Lambert GL, Moussa I, Fummi F, Pravadelli G (2005) An integrated design and verification methodology for reconfigurable multimedia system. In: Proc. of ACM\/IEEE DATE, pp\u00a0266\u2013271","DOI":"10.1109\/DATE.2005.61"},{"key":"5318_CR10","unstructured":"Cai L, Gajski D (2003) Transaction level modeling: an overview. In: Proc. of ACM\/IEEE CODES+ISSS, pp\u00a019\u201324"},{"issue":"1","key":"5318_CR11","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1145\/225871.225880","volume":"1","author":"K-T Cheng","year":"1996","unstructured":"Cheng K-T, Krishnakumar A (1996) Automatic generation of functional vectors using the extended finite state machine model. ACM TODAES 1(1):57\u201379","journal-title":"ACM TODAES"},{"key":"5318_CR12","unstructured":"Corno F, Cumani G, Sonza-Reorda M, Squillero G (2000) RT-level fault simulation techniques based on simulation command scripts. In: Proc. of IEEE DCIS, pp\u00a021\u201324"},{"key":"5318_CR13","doi-asserted-by":"crossref","unstructured":"Deniziak S, Sapiecha K (2004) Fast high-level fault simulator. In: Proc. of IEEE ICECS, pp\u00a0583\u2013586","DOI":"10.1109\/ICECS.2004.1399748"},{"issue":"6","key":"5318_CR14","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/MDT.2009.135","volume":"26","author":"L Dongwoo","year":"2009","unstructured":"Dongwoo L, Jongwhoa N (2009) A novel simulation fault injection method for dependability analysis. IEEE Des Test Comput 26(6):50\u201361","journal-title":"IEEE Des Test Comput"},{"key":"5318_CR15","doi-asserted-by":"crossref","unstructured":"Donlin A (2004) Transaction level modeling: Flows and use models. In: Proc. of ACM\/IEEE CODES + ISSS, pp\u00a075\u201380","DOI":"10.1145\/1016720.1016742"},{"key":"5318_CR16","doi-asserted-by":"crossref","unstructured":"Ecker W, Esen V, Schonberg L, Steininger T, Velten M, Hull M (2007) Impact of description languages, abstraction layer, and value representation on simulation performance. In: Proc. of ACM\/IEEE DATE, pp\u00a0767\u2013772","DOI":"10.1109\/DATE.2007.364688"},{"issue":"4","key":"5318_CR17","doi-asserted-by":"crossref","first-page":"400","DOI":"10.1109\/TR.2003.821926","volume":"52","author":"F Ferrandi","year":"2003","unstructured":"Ferrandi F, Fummi F, Pravadelli G, Sciuto D (2003) Identification of design errors through functional testing. IEEE Trans Reliab 52(4):400\u2013412","journal-title":"IEEE Trans Reliab"},{"key":"5318_CR18","unstructured":"Ghenassia F, Clouard A, Jain K, Maillet-Contoz L, Strassen J-P (2003) Using Transactional Level Models in a SoC Design Flow. Kluwer Academic Publishers"},{"issue":"3","key":"5318_CR19","doi-asserted-by":"crossref","first-page":"401","DOI":"10.1109\/43.913758","volume":"20","author":"I Ghosh","year":"2001","unstructured":"Ghosh I, Fujita M (2001) Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. IEEE Trans Comput-Aided Des Integr Circuits Syst 20(3):401\u2013415","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5318_CR20","doi-asserted-by":"crossref","unstructured":"Gracia J, Baraza JC, Gil D, Gil PJ (2001) Comparison and application of different VHDL-based fault injection techniques. In: Proc. of IEEE DFT, pp\u00a0579\u2013582","DOI":"10.1109\/DFTVS.2001.966775"},{"issue":"2","key":"5318_CR21","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1145\/1118537.1123073","volume":"31","author":"A Guerrouat","year":"2006","unstructured":"Guerrouat A, Richter H (2006) A component-based specification approach for embedded systems using FDTs. ACM SIGSOFT Softw Eng Notes 31(2):14\u201318","journal-title":"ACM SIGSOFT Softw Eng Notes"},{"key":"5318_CR22","doi-asserted-by":"crossref","unstructured":"Kammler D, Ascheid GJG, Leupers R, Meyr H (2009) A fast and flexible platform for fault injection and evaluation in Verilog-based simulations. In: Proc. of IEEE SSIRI, pp\u00a0309\u2013314","DOI":"10.1109\/SSIRI.2009.38"},{"key":"5318_CR23","doi-asserted-by":"crossref","unstructured":"Katagiri H, Yasumoto K, Kitajima A, Higashino T, Taniguchi K (2000) Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization. In: Proc. of ACM\/IEEE DAC, pp\u00a0762\u2013767","DOI":"10.1145\/337292.337771"},{"key":"5318_CR24","doi-asserted-by":"crossref","unstructured":"Koo TJ, Sinopoli B, Sangiovanni-Vincentelli A, Sastry S (1999) A formal approach to reactive system design: unmanned aerial vehicle flight management system design example. In: Proc. of IEEE CACSD, pp\u00a0522\u2013527","DOI":"10.1109\/CACSD.1999.808702"},{"issue":"11","key":"5318_CR25","doi-asserted-by":"crossref","first-page":"2526","DOI":"10.1109\/TCAD.2006.881333","volume":"25","author":"Z Liang","year":"2006","unstructured":"Liang Z, Ghosh I, Hsiao M (2006) A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage. IEEE Trans Comput-Aided Des Integr Circuits Syst 25(11):2526\u20132538","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5318_CR26","unstructured":"Mao W, Gulati RK (1996) Improving gate level fault coverage by RTL fault grading. In: Proc. of IEEE ITC, p\u00a0150"},{"key":"5318_CR27","doi-asserted-by":"crossref","unstructured":"Mingsong C, Mishra P, Kalita D (2007) Towards RTL test generation from SystemC TLM specifications. In: Proc. of IEEE HLDVT, pp\u00a091\u201396.","DOI":"10.1109\/HLDVT.2007.4392793"},{"key":"5318_CR28","doi-asserted-by":"crossref","unstructured":"Park S, Chen L, Parvathala PK, Patil S, Pomeranz I (2006) A functional coverage metric for estimating the gate-level fault coverage of functional tests. In: Proc. of IEEE ITC, pp\u00a01\u201310","DOI":"10.1109\/TEST.2006.297674"},{"key":"5318_CR29","unstructured":"Rimen M, Ohlsson J, Jenn E, Arlat J, Karlsson J (1994) Fault injection into VHDL models: the MEFISTO tool. In: Proc. of IEEE FTCS, pp\u00a066\u201375"},{"key":"5318_CR30","unstructured":"Su M-Y, Shih C-H, Huang J-D, Jou J-Y (2006) FSM-based transaction-level functional coverage for interface compliance verification. In: Proc. of ACM\/IEEE ASP-DAC, pp\u00a0448\u2013453"},{"key":"5318_CR31","unstructured":"Takach A, Gutberlet P, Waters S (2004) Fast bit-accurate C+\u2009+ datatypes for functional system verification and synthesis. In: Proc. of ECSI FDL, pp\u00a0337\u2013345"},{"issue":"8","key":"5318_CR32","doi-asserted-by":"crossref","first-page":"1104","DOI":"10.1109\/TCAD.2003.814958","volume":"22","author":"P Thaker","year":"2003","unstructured":"Thaker P, Agrawal V, Zaghloul M (2003) A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans Comput-Aided Des Integr Circuits Syst 22(8):1104\u20131113","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"5318_CR33","unstructured":"TLM-2.0 (2009) OSCI TLM-2.0 Language Reference Manual, Open SystemC Organization Initiative, http:\/\/www.accellera.org\/downloads\/standards\/ . Accessed 5 July 2012"},{"key":"5318_CR34","unstructured":"Tschche O, Sieh V, Balbach F (1997) VERIFY: Evaluation of reliability using VHDL-models with embedded fault descriptions. In: Proc. of IEEE FTCS, pp\u00a032\u201336"},{"key":"5318_CR35","unstructured":"Wang Z-H, Ye Y-Z (2005) The improvement for transaction level verification functional coverage. In: Proc. of IEEE ISCAS, pp\u00a05850\u20135853"},{"key":"5318_CR36","doi-asserted-by":"crossref","unstructured":"Zhong-hai W, Yi-zheng Y (2005) The improvement for transaction level verification functional coverage. In: Proc. of IEEE ISCAS, pp\u00a05850\u20135853","DOI":"10.1109\/ISCAS.2005.1465969"},{"issue":"1","key":"5318_CR37","first-page":"63","volume":"2","author":"A Zitouni","year":"2006","unstructured":"Zitouni A, Badrouchi S, Tourki R (2006) Communication architecture synthesis for multi-bus SoC. JCS 2(1):63\u201371","journal-title":"JCS"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-012-5318-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-012-5318-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-012-5318-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,2]],"date-time":"2019-07-02T16:32:46Z","timestamp":1562085166000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-012-5318-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7,22]]},"references-count":37,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2012,8]]}},"alternative-id":["5318"],"URL":"https:\/\/doi.org\/10.1007\/s10836-012-5318-z","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,7,22]]}}}