{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:02:38Z","timestamp":1781884958122,"version":"3.54.5"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2012,8,4]],"date-time":"2012-08-04T00:00:00Z","timestamp":1344038400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1007\/s10836-012-5322-3","type":"journal-article","created":{"date-parts":[[2012,8,13]],"date-time":"2012-08-13T21:04:14Z","timestamp":1344891854000},"page":"817-829","source":"Crossref","is-referenced-by-count":12,"title":["Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis"],"prefix":"10.1007","volume":"28","author":[{"given":"Vladimir","family":"Pasca","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lorena","family":"Anghel","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mounir","family":"Benabdenbi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2012,8,4]]},"reference":[{"key":"5322_CR1","doi-asserted-by":"crossref","unstructured":"Bernstein K, Andry P, Cann J et al (2007) Interconnects in the third dimension: design challenges for 3D ICs. Proceedings of the 44th Design Automation Conference, pp 562\u2013567","DOI":"10.1145\/1278480.1278623"},{"key":"5322_CR2","doi-asserted-by":"crossref","unstructured":"Cuviello M, Dey S, Bai X, Zhao Y (1999) Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects. Proceedings of International Conference on Computer-Aided Design (ICCAD), pp 297\u2013303","DOI":"10.1109\/ICCAD.1999.810665"},{"key":"5322_CR3","doi-asserted-by":"crossref","unstructured":"Emma PG, Kursur E et al (2008) Is 3D chip technology the next growth engine for performance improvement? IBM J Res Dev 52(6)","DOI":"10.1147\/JRD.2008.5388561"},{"key":"5322_CR4","doi-asserted-by":"crossref","unstructured":"Frank T, Frank T, Chappaz C et al (2010) Reliability approach of high density Through Silicon Via (TSV). Proceedings of 12th Electronics Packaging Technology Conference (EPTC), pp 312\u2013324","DOI":"10.1109\/EPTC.2010.5702655"},{"key":"5322_CR5","unstructured":"Goel P, McMahon MT (1982) Electronic Chip-in-Place Test. Proceedings of International Test Conference (ITC), pp 83\u201390"},{"key":"5322_CR6","unstructured":"Grange M, Weerasekera R, Pamunuwa D, Tenhunen H (2009) Examination of delay and signal integrity metrics in through silicon vias. Proceedings of 3D Integration Workshop, Design Automation and Test in Europe Conference(DATE), pp 89\u201392"},{"key":"5322_CR7","unstructured":"Huang Y-J, Li J-F, Chen J-J, Kwai D-M, Chou Y-F, Wu C-W (2011) A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. Proceedings of VLSI Test Symposium (VTS), pp 20\u201325"},{"key":"5322_CR8","doi-asserted-by":"crossref","unstructured":"Jarwala N, Yau CW (1989) A new framework for analyzing test generation and diagnosis algorithms for board interconnects. Proceedings of International Test Conference (ITC), pp 63\u201370","DOI":"10.1109\/TEST.1989.82278"},{"key":"5322_CR9","doi-asserted-by":"crossref","unstructured":"Jutman A (2004) At-speed on-chip diagnosis of board-level interconnect faults. Proceedings of European Test Symposium (ETS), pp 2\u20137","DOI":"10.1109\/ETSYM.2004.1347572"},{"key":"5322_CR10","doi-asserted-by":"crossref","unstructured":"Karmarkar AP, Xu XX, Moroz V (2009) Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV). Proceedings of International Reliability Physics Symposium (IRPS), pp 682\u2013687","DOI":"10.1109\/IRPS.2009.5173329"},{"issue":"4","key":"5322_CR11","doi-asserted-by":"crossref","first-page":"358","DOI":"10.1109\/T-C.1974.223950","volume":"23","author":"WH Kautz","year":"1974","unstructured":"Kautz WH (1974) Testing of faults in wiring interconnects. IEEE Trans Comput 23(4):358\u2013363","journal-title":"IEEE Trans Comput"},{"key":"5322_CR12","doi-asserted-by":"crossref","unstructured":"Leduc P, de Crecy F, Fayolle M, Charlet B, Enot T, Zussy M et al (2007) Challenges for 3D IC integration: bonding quality and thermal management. Proceedings of the IEEE International Interconnect Technology Conference (IITC), pp 210\u2013212","DOI":"10.1109\/IITC.2007.382392"},{"issue":"5","key":"5322_CR13","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1109\/MDT.2009.125","volume":"26","author":"H-HS Lee","year":"2009","unstructured":"Lee H-HS, Chakrabarty K (2009) Test challenges for 3D integrated circuits. IEEE Des Test Comput 26(5):26\u201335","journal-title":"IEEE Des Test Comput"},{"key":"5322_CR14","doi-asserted-by":"crossref","unstructured":"Liu X, Chen O, Dixit P, Chatterjee R, Tummala RR, Sitaraman SK (2009) Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV). Proceeding of 59th Electronic Components and Technology Conference (ECTC), pp 624\u2013629","DOI":"10.1109\/ECTC.2009.5074078"},{"key":"5322_CR15","doi-asserted-by":"crossref","unstructured":"Liu C, Song T, Cho J, Kim J, Kim J, Lim SK (2011) Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. Proceedings of the Design Automation Conference (DAC), pp 783\u2013788","DOI":"10.1145\/2024724.2024900"},{"key":"5322_CR16","doi-asserted-by":"crossref","unstructured":"Liu C, Song T, Lim SK (2011) Signal integrity analysis and optimization for 3D ICs. Proceedings of International Symposyum on Quality Electronic Design (ISQED), pp 42\u201349","DOI":"10.1109\/ISQED.2011.5770701"},{"key":"5322_CR17","doi-asserted-by":"crossref","unstructured":"Loi I, Angiolini F, Benini L (2008) Developing mesochronous synchronizers to enable 3D NoCs. Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp 1414\u20131419","DOI":"10.1145\/1403375.1403717"},{"key":"5322_CR18","doi-asserted-by":"crossref","unstructured":"Marinissen EJ (2010) Testing TSV-based three-dimensional stacked ICs. Proceedings of Design, Automation and Test in Europe (DATE) Conference, pp 1689\u20131694","DOI":"10.1109\/DATE.2010.5457087"},{"key":"5322_CR19","unstructured":"Marinissen EJ, Zorian Y (2009) Testing 3D chips containing through-silicon vias. Proceedings of International Test Conference (ITC), pp 1\u201311"},{"issue":"6","key":"5322_CR20","doi-asserted-by":"crossref","first-page":"1214","DOI":"10.1109\/JPROC.2006.873612","volume":"84","author":"R Patti","year":"2006","unstructured":"Patti R (2006) Three-dimensional integrated circuits and the future of System-on-Chip designs. Proc IEEE 84(6):1214\u20131224","journal-title":"Proc IEEE"},{"issue":"9","key":"5322_CR21","doi-asserted-by":"crossref","first-page":"1143","DOI":"10.1109\/43.945309","volume":"20","author":"R Pendurkar","year":"2001","unstructured":"Pendurkar R, Chatterjee A, Zorian Y (2001) Switching activity generation with automated BIST synthesis for performance testing of interconnects. IEEE Trans Comput-Aid Des Integr Circ Syst (TCAD) 20(9):1143\u20131158","journal-title":"IEEE Trans Comput-Aid Des Integr Circ Syst (TCAD)"},{"key":"5322_CR22","doi-asserted-by":"crossref","unstructured":"Sekar K, Dey S (2002) LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects. Proceedings of VLSI Test Symposium (VTS), pp 417\u2013422","DOI":"10.1109\/VTS.2002.1011174"},{"key":"5322_CR23","doi-asserted-by":"crossref","unstructured":"Topol AW et al (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4\/5)","DOI":"10.1147\/rd.504.0491"},{"key":"5322_CR24","unstructured":"Wagner PT (1987) Interconnect testing with boundary scan. Proceedings of International Test Conference (ITC), pp 52\u201357"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-012-5322-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-012-5322-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-012-5322-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,2]],"date-time":"2019-07-02T20:32:41Z","timestamp":1562099561000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-012-5322-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8,4]]},"references-count":24,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2012,12]]}},"alternative-id":["5322"],"URL":"https:\/\/doi.org\/10.1007\/s10836-012-5322-3","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,8,4]]}}}