{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,27]],"date-time":"2026-05-27T20:38:58Z","timestamp":1779914338244,"version":"3.53.1"},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2013,6,11]],"date-time":"2013-06-11T00:00:00Z","timestamp":1370908800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2013,8]]},"DOI":"10.1007\/s10836-013-5384-x","type":"journal-article","created":{"date-parts":[[2013,6,10]],"date-time":"2013-06-10T06:24:23Z","timestamp":1370845463000},"page":"537-544","source":"Crossref","is-referenced-by-count":12,"title":["High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design"],"prefix":"10.1007","volume":"29","author":[{"given":"Rahebeh","family":"Niaraki Asli","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Saeideh","family":"Shirinzadeh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2013,6,11]]},"reference":[{"key":"5384_CR1","doi-asserted-by":"crossref","first-page":"488","DOI":"10.1109\/TC.2011.31","volume":"61","author":"NDP Avirneni","year":"2012","unstructured":"Avirneni NDP, Somani AK (2012) Low overhead soft error mitigation techniques for high-performance and aggressive designs. IEEE Trans Comput 61:488\u2013501. doi: 10.1109\/TC.2011.31","journal-title":"IEEE Trans Comput"},{"key":"5384_CR2","doi-asserted-by":"crossref","first-page":"305","DOI":"10.1109\/TDMR.2005.853449","volume":"5","author":"RC Baumann","year":"2005","unstructured":"Baumann RC (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device and Materials Reliability. IEEE Trans Device Mater Reliab 5:305\u2013316. doi: 10.1109\/TDMR.2005.853449","journal-title":"IEEE Trans Device Mater Reliab"},{"key":"5384_CR3","unstructured":"Berkeley predictive technology model (2007) http:\/\/www.eas.asu.edu\/~ptm\/"},{"key":"5384_CR4","doi-asserted-by":"crossref","first-page":"2874","DOI":"10.1109\/23.556880","volume":"43","author":"T Calin","year":"1996","unstructured":"Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43:2874\u20132878. doi: 10.1109\/23.556880","journal-title":"IEEE Trans Nucl Sci"},{"key":"5384_CR5","unstructured":"Carreno VA, Choi G, and Iyer RK (1990) Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system. In NASA Tech Memorandum 4241"},{"key":"5384_CR6","doi-asserted-by":"crossref","unstructured":"Cha H, Patel JH (1993) A logic-level model for \u03b1-particle hits in CMOS circuits. Proc IEEE Int Conf Comput Des :538\u2013542. doi: 10.1.1.34.8586","DOI":"10.1109\/ICCD.1993.393319"},{"key":"5384_CR7","doi-asserted-by":"crossref","unstructured":"Chen M, Orailoglu A (2009) Flip-flop hardening and selection for soft error and delay fault resilience. In Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst :49\u201357. doi: 10.1109\/DFT.2009.50","DOI":"10.1109\/DFT.2009.50"},{"key":"5384_CR8","doi-asserted-by":"crossref","unstructured":"Choi Y, Kim Y, Lombardi F (2012) Soft error masking latch for sub-threshold voltage operation. In Proc IEEE Int Midwest Symp Circuits Syst :25\u201328. doi: 10.1109\/MWSCAS.2012.6291948","DOI":"10.1109\/MWSCAS.2012.6291948"},{"key":"5384_CR9","first-page":"583","volume":"50","author":"PE Dodd","year":"2003","unstructured":"Dodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Device Mat Rel 50:583\u2013602. doi: 10.1109\/TNS.2003.813129","journal-title":"IEEE Trans Device Mat Rel"},{"key":"5384_CR10","doi-asserted-by":"crossref","first-page":"1536","DOI":"10.1109\/JSSC.2004.831449","volume":"39","author":"P Hazucha","year":"2004","unstructured":"Hazucha P, Karnik T, Walstra S, Bloechel BA, Tschanz JW, Maiz J, Soumyanath K, Dermer GE, Narendra S, De V, Borkar S (2004) Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. IEEE J Solid State Circuits 39:1536\u20131543. doi: 10.1109\/CICC.2003.1249472","journal-title":"IEEE J Solid State Circuits"},{"key":"5384_CR11","doi-asserted-by":"crossref","first-page":"128","DOI":"10.1109\/TDSC.2004.14","volume":"1","author":"T Karnik","year":"2004","unstructured":"Karnik T, Hazucha P, Patel J (2004) Characterization of soft error caused by single event upsets in CMOS processes. IEEE Trans Depend Secure Comput 1:128\u2013143. doi: 10.1109\/TDSC.2004.14","journal-title":"IEEE Trans Depend Secure Comput"},{"key":"5384_CR12","doi-asserted-by":"crossref","first-page":"942","DOI":"10.1109\/4.58286","volume":"25","author":"L-S Kim","year":"1990","unstructured":"Kim L-S, Dutton RW (1990) Metastability of CMOS latch\/flip-flop. IEEE J Solid State Circuits 25:942\u2013951. doi: 10.1109\/4.58286","journal-title":"IEEE J Solid State Circuits"},{"key":"5384_CR13","doi-asserted-by":"crossref","first-page":"1315","DOI":"10.1109\/TVLSI.2010.2047954","volume":"19","author":"S Lin","year":"2011","unstructured":"Lin S, Kim YB, Lombardi F (2011) Design and performance evaluation of radiation hardened latches for nanoscale CMOS. IEEE Trans Large Scale Integr (VLSI) Syst 19:1315\u20131319. doi: 10.1109\/TVLSI.2010.2047954","journal-title":"IEEE Trans Large Scale Integr (VLSI) Syst"},{"key":"5384_CR14","doi-asserted-by":"crossref","unstructured":"Mitra S, Zhang M, Waqas S, Seifert N, Gill B, Kim KS (2006) Combinational logic soft error correction. In Proc IEEE Int\u2019l Test Conf :824\u2013832. doi: 10.1109\/TEST.2006.297681","DOI":"10.1109\/TEST.2006.297681"},{"key":"5384_CR15","doi-asserted-by":"crossref","unstructured":"Omana M, Rossi D, Metra C (2003) Novel transient fault hardened static latch. In Proc IEEE Int Test Conf :886\u2013892. doi: 10.1109\/TEST.2003.1271074","DOI":"10.1109\/TEST.2003.1271074"},{"key":"5384_CR16","doi-asserted-by":"crossref","first-page":"1255","DOI":"10.1109\/TC.2007.1070","volume":"56","author":"M Omana","year":"2007","unstructured":"Omana M, Rossi D, Metra C (2007) Latch susceptibility to transient faults and new hardening approach. IEEE Trans Comput 56:1255\u20131268. doi: 10.1109\/TC.2007.1070","journal-title":"IEEE Trans Comput"},{"key":"5384_CR17","unstructured":"Rey DM (2009) The MOSIS Service. http:\/\/www.mosis.org\/Technical\/Designrules\/scmos\/scmos-main.html"},{"key":"5384_CR18","doi-asserted-by":"crossref","unstructured":"Sasaki Y, Namba K, Ito H (2006) Soft error masking circuit and latch using Schmitt trigger circuit. In Proc IEEE DFT :327\u2013335. doi: 10.1109\/DFT.2006.60","DOI":"10.1109\/DFT.2006.60"},{"key":"5384_CR19","doi-asserted-by":"crossref","first-page":"3100","DOI":"10.1109\/TNS.2002.805402","volume":"49","author":"N Seifert","year":"2002","unstructured":"Seifert N, Zhu X, Massengill LW (2002) Impact of scaling on soft error rates in commercial microprocessors. IEEE Trans Nucl Sci 49:3100\u20133106. doi: 10.1109\/TNS.2002.805402","journal-title":"IEEE Trans Nucl Sci"},{"key":"5384_CR20","doi-asserted-by":"crossref","first-page":"778","DOI":"10.1109\/TVLSI.2003.814322","volume":"11","author":"V Zyuban","year":"2003","unstructured":"Zyuban V (2003) Optimization of scannable latches for low energy. IEEE Trans Very Large Scale Integr (VLSI) Syst 11:778\u2013788. doi: 10.1109\/TVLSI.2003.814322","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-013-5384-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-013-5384-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-013-5384-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,14]],"date-time":"2019-07-14T22:22:14Z","timestamp":1563142934000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-013-5384-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6,11]]},"references-count":20,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2013,8]]}},"alternative-id":["5384"],"URL":"https:\/\/doi.org\/10.1007\/s10836-013-5384-x","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,6,11]]}}}