{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T00:22:56Z","timestamp":1772065376437,"version":"3.50.1"},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2014,2,1]],"date-time":"2014-02-01T00:00:00Z","timestamp":1391212800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1007\/s10836-014-5432-1","type":"journal-article","created":{"date-parts":[[2014,2,11]],"date-time":"2014-02-11T22:30:49Z","timestamp":1392157849000},"page":"77-85","source":"Crossref","is-referenced-by-count":10,"title":["Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers"],"prefix":"10.1007","volume":"30","author":[{"given":"K. Murali","family":"Krishna","sequence":"first","affiliation":[]},{"given":"M.","family":"Sailaja","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,2,13]]},"reference":[{"issue":"5","key":"5432_CR1","doi-asserted-by":"crossref","first-page":"755","DOI":"10.1109\/TCAD.2009.2015736","volume":"28","author":"AS Abu-Issa","year":"2009","unstructured":"Abu-Issa AS, Quigley SF (2009) Bit-swapping LFSR and scan-chain ordering: a novel technique for peak- and average-power reduction in scan-based BIST. IEEE Trans Comput-Aided Des Integr Circ Syst 28(5):755\u2013759","journal-title":"IEEE Trans Comput-Aided Des Integr Circ Syst"},{"issue":"3","key":"5432_CR2","doi-asserted-by":"crossref","first-page":"356","DOI":"10.1109\/TVLSI.2009.2012511","volume":"18","author":"MH Abu-Rahma","year":"2010","unstructured":"Abu-Rahma MH, Anis M, Yoon SS (2010) Reducing SRAM power using fine-grained wordline pulse width control. IEEE Trans On Very Large Scale Integr (VLSI) Syst 18(3):356\u2013364","journal-title":"IEEE Trans On Very Large Scale Integr (VLSI) Syst"},{"issue":"II","key":"5432_CR3","first-page":"52","volume":"III","author":"AN Awad","year":"2007","unstructured":"Awad AN, Abu-Issa AS (2007) Low power address generator for memory built-in self test. Res Bull Jordan ACM III(II):52\u201356","journal-title":"Res Bull Jordan ACM"},{"issue":"7","key":"5432_CR4","doi-asserted-by":"crossref","first-page":"2196","DOI":"10.1109\/TIM.2009.2013668","volume":"58","author":"C-L Hsu","year":"2009","unstructured":"Hsu C-L, Chen T-H (2009) Built-in self-test design for fault detection and fault diagnosis in SRAM-based FPGA. IEEE Trans Instrum Meas 58(7):2196\u20132208","journal-title":"IEEE Trans Instrum Meas"},{"key":"5432_CR5","doi-asserted-by":"crossref","unstructured":"Kumar TN, Lombardi F (2013) A novel heuristic method for application-dependent testing of a SRAM-based FPGA interconnect. IEEE Trans Comput 62(1):163\u2013172","DOI":"10.1109\/TC.2011.247"},{"key":"5432_CR6","doi-asserted-by":"crossref","first-page":"722","DOI":"10.1109\/DATE.2005.92","volume":"52","author":"EJ Marinissen","year":"2005","unstructured":"Marinissen EJ, Prince B, Keitel-Schulz D, Zorian Y (2005) Challenges in embedded memory design and test. Proc Design Autom Test Eur 52:722\u2013727","journal-title":"Proc Design Autom Test Eur"},{"issue":"3","key":"5432_CR7","doi-asserted-by":"crossref","first-page":"299","DOI":"10.1109\/92.845896","volume":"8","author":"L Benini","year":"2000","unstructured":"Benini L, Bogliolo A, De Micheli G (2000) A survey of design techniques for system-level dynamic power management. IEEE Trans Very Large Scale Integr (VLSI) Syst 8(3):299\u2013316","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"issue":"7","key":"5432_CR8","doi-asserted-by":"crossref","first-page":"1072","DOI":"10.1109\/TCAD.2011.2127030","volume":"30","author":"N Mukherjee","year":"2011","unstructured":"Mukherjee N, Pogiel A, Rajski J, Tyszer J (2011) BIST-based fault diagnosis for read-only memories. IEEE Trans Comput-Aided Des Integr Circ Syst 30(7):1072\u20131085","journal-title":"IEEE Trans Comput-Aided Des Integr Circ Syst"},{"key":"5432_CR9","first-page":"1","volume":"7","author":"R Muthammal","year":"2011","unstructured":"Muthammal R, Joseph DRKO (2011) Low power efficient built in self test. Proc IEEE Int Conf Microwaves Commun Antennas Electron Syst 7:1\u20135","journal-title":"Proc IEEE Int Conf Microwaves Commun Antennas Electron Syst"},{"key":"5432_CR10","unstructured":"NishaHaridas M, Devi N (2011) Efficient linear feedback shift register design for pseudo exhaustive test. Int J Electron Comput Technol 1:350\u2013354"},{"key":"5432_CR11","doi-asserted-by":"crossref","unstructured":"Noor NQ, Yusof Y, Sparon A (2009) Low area FSM-based memory BIST for synchronous SRAM. Proceedings of the international colloquium of Signal Processing and Its application, Kuala Lumpur, pp 409\u2013412","DOI":"10.1109\/CSPA.2009.5069261"},{"issue":"12","key":"5432_CR12","first-page":"808","volume":"92","author":"Y Park","year":"2009","unstructured":"Park Y, Park J, Han T, Kang S (2009) An effective programmable memory bist for embedded memory. IEICE Trans Inf Syst 92(12):808\u2013818","journal-title":"IEICE Trans Inf Syst"},{"issue":"5","key":"5432_CR13","first-page":"1","volume":"1","author":"C Ravishankar-Reddy","year":"2012","unstructured":"Ravishankar-Reddy C, Zilani S, Sumalatha V (2012) Low power, Low-transition random pattern generator. Int J Eng Res Technol (IJERT) 1(5):1\u20136","journal-title":"Int J Eng Res Technol (IJERT)"},{"key":"5432_CR14","doi-asserted-by":"crossref","unstructured":"Saraswathi T, Ragini K, Ganapathy Reddy C (2011) A review on power optimization of linear feedback shift register (LFSR) for low power built In self test (BIST). Int J Electronics Comput Technol 6:172\u2013176","DOI":"10.1109\/ICECTECH.2011.5942075"},{"key":"5432_CR15","unstructured":"Sharma C (2011) Power reduction in VLSI chips by optimizing switching activity at test process, architecture & gate level. Int J Eng Sci Tech (IJEST) 3(4):3256\u20133259"},{"key":"5432_CR16","doi-asserted-by":"crossref","unstructured":"Tehranipoor M, Nourani M, Ahmed N (2005) Low transition LFSR for BIST-based applications. Proceedings of the 14th Asian Test Symposium, pp 138\u2013143","DOI":"10.1109\/ATS.2005.77"},{"key":"5432_CR17","doi-asserted-by":"crossref","unstructured":"Van de Goor AdJ, Kukner H, Hamdioui S (2011) Optimizing memory BIST address generator implementations. 6th international conference on design & technology of integrated systems in nanoscale Era, pp 1\u20136, April","DOI":"10.1109\/DTIS.2011.5941430"},{"issue":"7","key":"5432_CR18","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TCAD.2002.1013896","volume":"21","author":"S Wang","year":"2002","unstructured":"Wang S, Gupta SK (2002) DS-LFSR: a BIST TPG for Low switching activity. IEEE Trans Comput-Aided Des Integr Circ Syst 21(7):3","journal-title":"IEEE Trans Comput-Aided Des Integr Circ Syst"},{"key":"5432_CR19","unstructured":"Wang W-L, Lee KJ (2005) A complete memory address generator for scan based march algorithms. Proceedings of the 2005 I.E. international workshop on memory technology, design, and testing (MTDT\u201905), Taipei, pp 83\u201388"},{"key":"5432_CR20","unstructured":"Yarmolik SV, Yarmolik VN (2006) Modified gray and counter sequences for memory test address generation. Proceedings of International Conference MIXDES 2006 Gdynia, Poland, pp 572\u2013576"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5432-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-014-5432-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5432-1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T10:53:20Z","timestamp":1565175200000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-014-5432-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":20,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2014,2]]}},"alternative-id":["5432"],"URL":"https:\/\/doi.org\/10.1007\/s10836-014-5432-1","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,2]]}}}