{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T20:10:09Z","timestamp":1746303009434,"version":"3.40.4"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2014,7,12]],"date-time":"2014-07-12T00:00:00Z","timestamp":1405123200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1007\/s10836-014-5463-7","type":"journal-article","created":{"date-parts":[[2014,7,11]],"date-time":"2014-07-11T06:03:34Z","timestamp":1405058614000},"page":"425-442","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs"],"prefix":"10.1007","volume":"30","author":[{"given":"Anees","family":"Ullah","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Sterpone","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2014,7,12]]},"reference":[{"key":"5463_CR1","first-page":"101","volume-title":"\u201cEvaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs,\u201d","author":"JR Azambuja","year":"2009","unstructured":"Azambuja JR, Sousa F, Rosa L, Kastensmidt FL (2009) \u201cEvaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs,\u201d. In On-Line Testing Symposium, Sesimbra, pp 101\u2013106"},{"issue":"4","key":"5463_CR2","doi-asserted-by":"crossref","first-page":"2259","DOI":"10.1109\/TNS.2008.2001422","volume":"55","author":"M Berg","year":"2008","unstructured":"Berg M, Poivey C, Petrick D et al (2008) \"Effectiveness of internal versus external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design, test, and analysis,\". IEEE Trans on Nucl Sci 55(4):2259\u20132266","journal-title":"IEEE Trans on Nucl Sci"},{"key":"5463_CR3","unstructured":"Boost C++ libraries. [Online]. www.boost.org"},{"key":"5463_CR4","unstructured":"Carmichael C (2001) \u201cTriple module redundancy design techniques for Virtex FPGAs,\u201d Xilinx Inc., XAPP197 (V1.0), November"},{"key":"5463_CR5","unstructured":"Carmichael C, Caffrey M, Salazar A (2000) Correcting single event upsets through virtex partial reconfiguration XAPP216 v1.0"},{"key":"5463_CR6","volume-title":"\"Guaranteed Fault Recovery Time for FPGA- based TMR Circuits Employing Partial Reconfiguration,\" in 2nd International Workshop on Computing in Heterogeneous","author":"E Cetin","year":"2012","unstructured":"Cetin E, Diessel O (2012) \"Guaranteed Fault Recovery Time for FPGA- based TMR Circuits Employing Partial Reconfiguration,\" in 2nd International Workshop on Computing in Heterogeneous. Autonomous \u2018N\u2019 Goal-oriented Environments, San Francisco"},{"key":"5463_CR7","unstructured":"Champman K, Jones L (2009) SEU strategies for Virtex-5 devices, Xilinx Inc., XAPP864"},{"key":"5463_CR8","unstructured":"Constraints Guide. Xilinx Inc. [Online]. http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx14_\/cgd.pdf"},{"issue":"1","key":"5463_CR9","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1016\/S0026-2714(99)00225-5","volume":"40","author":"DM Fleetwood","year":"2000","unstructured":"Fleetwood DM, Peter S, Winokurb, Doddb PE (2000) \u201cAn overview of radiation effects on electronics in the space telecommunications environment,\u201d. Microelectron Reliab 40(1):17\u201326","journal-title":"Microelectron Reliab"},{"key":"5463_CR10","first-page":"85","volume-title":"\u201cOnline clock routing in Xilinx FPGAs for High performance and reliability,\u201d","author":"X Iturbe","year":"2012","unstructured":"Iturbe X, Benkrid K, Torrego R, Ebrahim A, Arslan T (2012) \u201cOnline clock routing in Xilinx FPGAs for High performance and reliability,\u201d. In IEEE Adaptive Hardware Systems, Erlangen, pp 85\u201391"},{"key":"5463_CR11","unstructured":"Jedec Standard (2006) \u201cMeasurement and reporting of alpha particle and terrestrial cosmi ray-induced soft errors in semiconductor devices,\u201d Tech. Rep JESD89A, [Online]. http:\/\/www.jedec.org\/sites\/default\/?les\/docs\/jesd89a.pdf"},{"key":"5463_CR12","doi-asserted-by":"crossref","unstructured":"Nazar GL (2013) \u201cFine-Grain Error Detection Techniques for Fast Repair of FPGAs\u201d, Phd Dissertation, UFRGS, [Online]. http:\/\/www.lume.ufrgs.br\/bitstream\/handle\/10183\/77746\/000897120.pdf?sequence=1","DOI":"10.1109\/CASES.2013.6662506"},{"key":"5463_CR13","first-page":"149","volume-title":"\u201cExploiting Modified Placement and Hardwired Rescources to Provide High Reliability in FPGAs,\u201d","author":"GL Nazar","year":"2012","unstructured":"Nazar GL, Carro L (2012) \u201cExploiting Modified Placement and Hardwired Rescources to Provide High Reliability in FPGAs,\u201d. In 20th International Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, pp 149\u2013152"},{"key":"5463_CR14","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4419-6993-4","volume-title":"Soft Errors in Modern Electronic Systems","author":"M Nicolaidis","year":"2011","unstructured":"Nicolaidis M (2011) Soft Errors in Modern Electronic Systems. Springer, US"},{"key":"5463_CR15","unstructured":"Open Cores Repository. [Online]. opencores.org"},{"key":"5463_CR16","first-page":"199","volume-title":"\u201cSynchronizing triple modular redundant designs in dynamic partial reconfiguration applications,\u201d","author":"C Pilotto","year":"2008","unstructured":"Pilotto C, Azambuja JR, Kastensmidt LF (2008) \u201cSynchronizing triple modular redundant designs in dynamic partial reconfiguration applications,\u201d. In ACM 21st annual symposium on Integrated circuits and system design (SBCCI\u201908), Gramado, pp 199\u2013204"},{"issue":"6","key":"5463_CR17","doi-asserted-by":"crossref","first-page":"2037","DOI":"10.1109\/TNS.2007.910870","volume":"54","author":"H Quinn","year":"2007","unstructured":"Quinn H, Morgan K, Graham P et al (2007) Domain Crossing Errors: Limitations on Single Device Triple Modular Redundancy Circuits in Xilinx FPGAs. IEEE Trans Nucl Sci 54(6):2037\u20132043","journal-title":"IEEE Trans Nucl Sci"},{"key":"5463_CR18","first-page":"1","volume-title":"\u201cAn error-detection and self-repairing for dynamically and partially reconfigurable systems,\u201d","author":"MS Reorda","year":"2013","unstructured":"Reorda MS, Sterpone L, Ullah A (2013) \u201cAn error-detection and self-repairing for dynamically and partially reconfigurable systems,\u201d. In IEEE Europen Testing Symposium, Avignon, pp 1\u20137"},{"key":"5463_CR19","first-page":"99","volume-title":"\u201cFPGA partial reconfiguration via configuration scrubbing,\u201d","author":"B Sellers","year":"2009","unstructured":"Sellers B, Wirthlin M, Kalb J (2009) \u201cFPGA partial reconfiguration via configuration scrubbing,\u201d. In Field Programmable Logic and Applications, Prague, pp 99\u2013104"},{"key":"5463_CR20","first-page":"41","volume-title":"\u201cTorc: Towards an Open-Source Tool Flow,\u201d","author":"N Steiner","year":"2011","unstructured":"Steiner N, Wood A, Shojaei H et al (2011) \u201cTorc: Towards an Open-Source Tool Flow,\u201d. In Proceeding of 19th ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, pp 41\u201344"},{"key":"5463_CR21","first-page":"9","volume-title":"\"On the optimal reconfiguration times of TMR circuits on SRAM based FPGAs,\"","author":"L Sterpone","year":"2013","unstructured":"Sterpone L, Ullah A (2013) \"On the optimal reconfiguration times of TMR circuits on SRAM based FPGAs,\". In NASA\/ESA Adaptive Hardware Systems, Torino, pp 9\u201314"},{"key":"5463_CR22","doi-asserted-by":"crossref","unstructured":"Sterpone L, Violante M (December 2005) A new analytical approach to estimate the effects of SEU in TMR architectures implemented through SRAM based FPGAs. IEEE Trans Nucl Sci 52(6):2217\u20132223","DOI":"10.1109\/TNS.2005.860745"},{"key":"5463_CR23","unstructured":"Virtex-5 configuration user guide. Xilinx Inc. [Online]. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug191.pdf"},{"key":"5463_CR24","unstructured":"Virtex-5 FPGA User Guide. (2012) Xilinx Inc. [Online]. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug190.pdf"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5463-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-014-5463-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5463-7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T19:29:04Z","timestamp":1746300544000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-014-5463-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7,12]]},"references-count":24,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,8]]}},"alternative-id":["5463"],"URL":"https:\/\/doi.org\/10.1007\/s10836-014-5463-7","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2014,7,12]]}}}