{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,4]],"date-time":"2025-05-04T14:40:07Z","timestamp":1746369607683,"version":"3.40.4"},"reference-count":17,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2014,9,7]],"date-time":"2014-09-07T00:00:00Z","timestamp":1410048000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1007\/s10836-014-5475-3","type":"journal-article","created":{"date-parts":[[2014,9,6]],"date-time":"2014-09-06T05:39:16Z","timestamp":1409981956000},"page":"629-635","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs"],"prefix":"10.1007","volume":"30","author":[{"given":"Zhigang","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lianping","family":"Guo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shulin","family":"Tian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tao","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2014,9,7]]},"reference":[{"key":"5475_CR1","doi-asserted-by":"crossref","first-page":"1022","DOI":"10.1109\/JSSC.1980.1051512","volume":"15","author":"WC Black Jr","year":"1980","unstructured":"Black WC Jr, Hodges D (1980) Time interleaved converter arrays. IEEE J Solid State Circuits 15:1022\u20131029","journal-title":"IEEE J Solid State Circuits"},{"key":"5475_CR2","doi-asserted-by":"crossref","unstructured":"H. Cheng-Chung, H. Fong-Ching, S. Chih-Yung, H. Chen-Chih, L. Ying-Hsi, C.-C. Lee, et al. (2007) \u201cAn 11b 800MS\/s Time-Interleaved ADC with Digital Background Calibration,\u201d in IEEE International Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers, pp. 464\u2013615","DOI":"10.1109\/ISSCC.2007.373495"},{"key":"5475_CR3","doi-asserted-by":"crossref","first-page":"2091","DOI":"10.1109\/JSSC.2010.2061630","volume":"45","author":"L Chi Ho","year":"2010","unstructured":"Chi Ho L, Hurst PJ, Lewis SH (2010) A four-channel time-interleaved adc with digital calibration of interchannel timing and memory errors. IEEE J Solid State Circuits 45:2091\u20132103","journal-title":"IEEE J Solid State Circuits"},{"key":"5475_CR4","doi-asserted-by":"crossref","first-page":"1912","DOI":"10.1109\/4.735531","volume":"33","author":"KC Dyer","year":"1998","unstructured":"Dyer KC, Fu D, Lewis SH, Hurst PJ (1998) An analog background calibration technique for time-interleaved analog-to-digital converters. IEEE J Solid State Circuits 33:1912\u20131919","journal-title":"IEEE J Solid State Circuits"},{"key":"5475_CR5","first-page":"3913","volume":"6","author":"J Elbornsson","year":"2001","unstructured":"Elbornsson J, Eklund JE (2001) Blind estimation of timing errors in interleaved AD converters,\u201d in 2001 I.E. International Conference on Acoustics, Speech, and Signal Processing, 2001. Proceedings (ICASSP \u201901) 6:3913\u20133916","journal-title":"Proceedings (ICASSP \u201901)"},{"key":"5475_CR6","doi-asserted-by":"crossref","unstructured":"J. Elbornsson, K. Folkesson, and J. E. Eklund (2002) \u201cMeasurement verification of estimation method for time errors in a time-interleaved A\/D converter system,\u201d in IEEE International Symposium on Circuits and Systems, 2002. ISCAS 2002, pp. III-129-III-132 vol.3","DOI":"10.1109\/ISCAS.2002.1010177"},{"key":"5475_CR7","doi-asserted-by":"crossref","first-page":"1904","DOI":"10.1109\/4.735530","volume":"33","author":"D Fu","year":"1998","unstructured":"Fu D, Dyer KC, Lewis SH, Hurst PJ (1998) A digital background calibration technique for time-interleaved analog-to-digital converters. IEEE J Solid State Circuits 33:1904\u20131911","journal-title":"IEEE J Solid State Circuits"},{"key":"5475_CR8","doi-asserted-by":"crossref","first-page":"2650","DOI":"10.1109\/JSSC.2006.884331","volume":"41","author":"SK Gupta","year":"2006","unstructured":"Gupta SK, Inerfield MA, Jingbo W (2006) A 1-GS\/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture. IEEE J Solid State Circuits 41:2650\u20132657","journal-title":"IEEE J Solid State Circuits"},{"key":"5475_CR9","doi-asserted-by":"crossref","first-page":"863","DOI":"10.1109\/TCSI.2006.888770","volume":"54","author":"S Huang","year":"2007","unstructured":"Huang S, Levy BC (2007) Blind calibration of timing offsets for four-channel time-interleaved ADCs. IEEE Trans Circ Syst I Regul Pap 54:863\u2013876","journal-title":"IEEE Trans Circ Syst I Regul Pap"},{"key":"5475_CR10","doi-asserted-by":"crossref","first-page":"603","DOI":"10.1109\/82.850419","volume":"47","author":"J Huawen","year":"2000","unstructured":"Huawen J, Lee EKF (2000) A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs. IEEE Trans Circ Syst II Analog Digit Signal Process 47:603\u2013613","journal-title":"IEEE Trans Circ Syst II Analog Digit Signal Process"},{"key":"5475_CR11","doi-asserted-by":"crossref","first-page":"1618","DOI":"10.1109\/JSSC.2002.804327","volume":"37","author":"SM Jamal","year":"2002","unstructured":"Jamal SM, Fu D, Chang NCJ, Hurst PJ, Lewis SH (2002) A 10-b 120-Msample\/s time-interleaved analog-to-digital converter with digital background calibration. IEEE J Solid State Circuits 37:1618\u20131627","journal-title":"IEEE J Solid State Circuits"},{"key":"5475_CR12","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1109\/TCSI.2003.821302","volume":"51","author":"SM Jamal","year":"2004","unstructured":"Jamal SM, Fu D, Singh MP, Hurst PJ, Lewis SH (2004) Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter. IEEE Trans Circ Syst I Regul Pap 51:130\u2013139","journal-title":"IEEE Trans Circ Syst I Regul Pap"},{"key":"5475_CR13","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1109\/19.50419","volume":"39","author":"YC Jenq","year":"1990","unstructured":"Jenq YC (1990) Digital spectra of nonuniformly sampled signals: a robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving. IEEE Trans Instrum Meas 39:71\u201375","journal-title":"IEEE Trans Instrum Meas"},{"key":"5475_CR14","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1109\/81.915383","volume":"48","author":"N Kurosawa","year":"2001","unstructured":"Kurosawa N, Kobayashi H, Maruyama K, Sugawara H, Kobayashi K (2001) Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Trans Circ Syst I Fundam Theory Appl 48:261\u2013271","journal-title":"IEEE Trans Circ Syst I Fundam Theory Appl"},{"key":"5475_CR15","doi-asserted-by":"crossref","first-page":"1072","DOI":"10.1109\/TMTT.2005.843487","volume":"53","author":"S Munkyo","year":"2005","unstructured":"Munkyo S, Rodwell MJW, Madhow U (2005) Comprehensive digital correction of mismatch errors for a 400-msamples\/s 80-dB SFDR time-interleaved analog-to-digital converter. IEEE Trans Microw Theory Tech 53:1072\u20131082","journal-title":"IEEE Trans Microw Theory Tech"},{"key":"5475_CR16","doi-asserted-by":"crossref","first-page":"405","DOI":"10.2478\/v10178-010-0034-4","volume":"XVII","author":"H Pan","year":"2010","unstructured":"Pan H, Tian S, Ye P (2010) \u201cAn adaptive synthesis calibration method for time-interleaved sampling systems,\u201d. Metrol Meas Syst XVII:405\u2013414","journal-title":"Metrol Meas Syst"},{"key":"5475_CR17","doi-asserted-by":"crossref","first-page":"423","DOI":"10.1109\/TIM.2004.823321","volume":"53","author":"JMD Pereira","year":"2004","unstructured":"Pereira JMD, Girao PMBS, Serra AMC (2004) An FFT-based method to evaluate and compensate gain and offset errors of interleaved ADC systems. IEEE Trans Instrum Meas 53:423\u2013430","journal-title":"IEEE Trans Instrum Meas"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5475-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-014-5475-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5475-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,4]],"date-time":"2025-05-04T14:14:53Z","timestamp":1746368093000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-014-5475-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9,7]]},"references-count":17,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2014,10]]}},"alternative-id":["5475"],"URL":"https:\/\/doi.org\/10.1007\/s10836-014-5475-3","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2014,9,7]]}}}