{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,19]],"date-time":"2024-07-19T05:53:41Z","timestamp":1721368421179},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2014,10,18]],"date-time":"2014-10-18T00:00:00Z","timestamp":1413590400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1007\/s10836-014-5484-2","type":"journal-article","created":{"date-parts":[[2014,10,17]],"date-time":"2014-10-17T06:23:46Z","timestamp":1413527026000},"page":"711-723","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":21,"title":["Access Port Protection for Reconfigurable Scan Networks"],"prefix":"10.1007","volume":"30","author":[{"given":"Rafal","family":"Baranowski","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2014,10,18]]},"reference":[{"issue":"3","key":"5484_CR1","doi-asserted-by":"crossref","first-page":"216","DOI":"10.1109\/MDT.2008.77","volume":"25","author":"M Abramovici","year":"2008","unstructured":"Abramovici M (2008) In-system silicon validation and debug. IEEE Design & Test Comput 25(3):216\u2013223","journal-title":"IEEE Design & Test Comput"},{"key":"5484_CR2","first-page":"966","volume":"7","author":"K Agarwal","year":"2011","unstructured":"Agarwal K (2011) Secure scan design. Us Patent App. 7:966\u2013 535","journal-title":"Us Patent App."},{"key":"5484_CR3","volume-title":"Reconfigurable scan networks: formal verification, access optimization and protection","author":"R Baranowski","year":"2014","unstructured":"Baranowski R (2014) Reconfigurable scan networks: formal verification, access optimization and protection. University of Stuttgart, PhD thesis. http:\/\/elib.uni-stuttgart.de\/opus\/volltexte\/2014\/8982"},{"key":"5484_CR4","doi-asserted-by":"crossref","unstructured":"Baranowski R, Kochte MA, Wunderlich HJ (2012) Modeling, verification and pattern generation for reconfigurable scan networks. In: Proceedings of IEEE International Test Conference (ITC), paper 8.2","DOI":"10.1109\/TEST.2012.6401555"},{"key":"5484_CR5","doi-asserted-by":"crossref","unstructured":"Baranowski R, Kochte MA, Wunderlich HJ (2013) Scan pattern retargeting and merging with reduced access time. In: Proceedings of IEEE European Test Symposium (ETS), pp 39\u201345","DOI":"10.1109\/ETS.2013.6569354"},{"key":"5484_CR6","doi-asserted-by":"crossref","unstructured":"Baranowski R, Kochte MA, Wunderlich HJ (2013) Securing access to reconfigurable scan networks. In: Proceedings of IEEE Asian Test Symposium (ATS), pp 295\u2013300","DOI":"10.1109\/ATS.2013.61"},{"key":"5484_CR7","doi-asserted-by":"crossref","unstructured":"Buskey R, Frosik B (2006) Protected JTAG. In: Proceedings of IEEE International Conference on Parallel Processing Workshops (ICCPW), pp 405\u2013414","DOI":"10.1109\/ICPPW.2006.65"},{"issue":"1","key":"5484_CR8","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1109\/TVLSI.2010.2089071","volume":"20","author":"GM Chiu","year":"2012","unstructured":"Chiu GM, Li JM (2012) A secure test wrapper design against internal and boundary scan attacks for embedded cores. IEEE Trans on Very Large Scale Integration (VLSI) Systems 20 (1):126\u2013134","journal-title":"IEEE Trans on Very Large Scale Integration (VLSI) Systems"},{"key":"5484_CR9","doi-asserted-by":"crossref","unstructured":"Clark C (2010) Anti-Tamper JTAG TAP design enables DRM to JTAG registers and P1687 On-Chip instruments. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp 19\u201324","DOI":"10.1109\/HST.2010.5513119"},{"key":"5484_CR10","doi-asserted-by":"crossref","unstructured":"Da Rolt J, Das A, Di Natale G, Flottes ML, Rouzeyre B, Verbauwhede I (2014) Test versus security: past and present. To appear in: IEEE Trans on Emerging Topics in Computing","DOI":"10.1109\/TETC.2014.2304492"},{"issue":"2","key":"5484_CR11","doi-asserted-by":"crossref","first-page":"193","DOI":"10.1007\/s10836-013-5369-9","volume":"29","author":"A Das","year":"2013","unstructured":"Das A, Rolt J, Ghosh S, Seys S, Dupuis S, Natale G, Flottes ML, Rouzeyre B, Verbauwhede I (2013) Secure JTAG implementation using schnorr protocol. J Electron Test (JETTA) 29(2):193\u2013209","journal-title":"J Electron Test (JETTA)"},{"key":"5484_CR12","doi-asserted-by":"crossref","unstructured":"Dworak J, Crouch A, Potter J, Zygmontowicz A, Thornton M (2013) Don\u2019t forget to lock your SIB: hiding instruments using P1687. In: Proceedings of IEEE International Test Conference (ITC), paper, vol 6, p 2","DOI":"10.1109\/TEST.2013.6651903"},{"issue":"12","key":"5484_CR13","doi-asserted-by":"crossref","first-page":"1755","DOI":"10.1016\/j.mejo.2009.09.007","volume":"40","author":"E Ebrard","year":"2009","unstructured":"Ebrard E, Allard B, Candelier P, Waltz P (2009) Review of fuse and antifuse solutions for advanced standard CMOS technologies. Microelectron J 40(12):1755\u20131765","journal-title":"Microelectron J"},{"key":"5484_CR14","doi-asserted-by":"crossref","unstructured":"Eklow B, Bennetts B (2006) New techniques for accessing embedded instrumentation: IEEE P1687 (IJTAG). In: Proceedings of IEEE European Test Symposium (ETS), pp 253\u2013254","DOI":"10.1109\/ETS.2006.33"},{"issue":"10","key":"5484_CR15","doi-asserted-by":"crossref","first-page":"1459","DOI":"10.1109\/TC.2011.155","volume":"61","author":"F Ghani Zadegan","year":"2012","unstructured":"Ghani Zadegan F, Ingelsson U, Carlsson G, Larsson E (2012) Access time analysis for IEEE P1687. IEEE Trans Comput 61(10):1459\u20131472","journal-title":"IEEE Trans Comput"},{"key":"5484_CR16","doi-asserted-by":"crossref","unstructured":"Hely D, Flottes ML, Bancel F, Rouzeyre B, Berard N, Renovell M (2004) Scan design and secure chip [Secure IC Testing]. In: Proceedings of IEEE On-Line Testing Symposium (IOLTS), pp 219\u2013224","DOI":"10.1109\/OLT.2004.1319691"},{"key":"5484_CR17","unstructured":"IEEE (2013) IEEE Standard for test access port and boundary-scan architecture 1149.1-2013. Test Technology Technical Committee of the IEEE Computer Society, USA"},{"key":"5484_CR18","unstructured":"K\u00f6mmerling O, Kuhn MG (1999) Design principles for tamper-resistant smartcard processors. In: Proceedings of USENIX Workshop on Smartcard Technology. USENIX Association, WOST, pp 9\u201320"},{"key":"5484_CR19","doi-asserted-by":"crossref","unstructured":"Larsson E, Ghani Zadegan F (2012) Accessing embedded DfT instruments with IEEE P1687. In: Proceedings of IEEE Asian Test Symposium (ATS), pp 71\u201376","DOI":"10.1109\/ATS.2012.74"},{"key":"5484_CR20","doi-asserted-by":"crossref","unstructured":"Lee J, Tehranipoor M, Plusquellic J (2006) A low-cost solution for protecting IPs against scan-based side-channel attacks. In: Proceedings of IEEE VLSI Test Symposium (VTS), pp 94\u201399","DOI":"10.1109\/VTS.2006.7"},{"issue":"4","key":"5484_CR21","doi-asserted-by":"crossref","first-page":"325","DOI":"10.1109\/TDSC.2007.70215","volume":"4","author":"J Lee","year":"2007","unstructured":"Lee J, Tehranipoor M, Patel C, Plusquellic J (2007) Securing designs against scan-based side-channel attacks. IEEE Trans on Dependable and Secure Computing 4(4):325\u2013336","journal-title":"IEEE Trans on Dependable and Secure Computing"},{"key":"5484_CR22","doi-asserted-by":"crossref","unstructured":"Ley A (2009) Doing more with less\u2014an IEEE 1149.7 embedded tutorial: standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture. In: Proceedings of IEEE International Test Conference (ITC), paper ET3.1","DOI":"10.1109\/TEST.2009.5355572"},{"key":"5484_CR23","doi-asserted-by":"crossref","unstructured":"Marinissen E, Iyengar V, Chakrabarty K (2002) A set of benchmarks for modular testing of SOCs. In: Proceedings of IEEE International Test Conference (ITC), pp 519\u2013528","DOI":"10.1109\/TEST.2002.1041802"},{"key":"5484_CR24","doi-asserted-by":"crossref","unstructured":"Nicolaidis M, Noraz S, Courtois B (1989) A generalized theory of fail-safe systems. In: International Symposium on Fault-Tolerant Computing. FTCS, Digest of Papers, pp 398\u2013406","DOI":"10.1109\/FTCS.1989.105602"},{"key":"5484_CR25","doi-asserted-by":"crossref","first-page":"549","DOI":"10.1007\/s10836-010-5170-y","volume":"26","author":"K Park","year":"2010","unstructured":"Park K, Yoo S, Kim T, Kim J (2010) JTAG security system based on credentials. J Electron Test (JETTA) 26:549\u2013557","journal-title":"J Electron Test (JETTA)"},{"issue":"2","key":"5484_CR26","doi-asserted-by":"crossref","first-page":"240","DOI":"10.5573\/JSTS.2012.12.2.240","volume":"12","author":"KY Park","year":"2012","unstructured":"Park KY, Yoo SG, Kim J (2012) Debug port protection mechanism for secure embedded devices. IEEE J Semicond Tech Sci 12(2):240\u2013253","journal-title":"IEEE J Semicond Tech Sci"},{"issue":"7","key":"5484_CR27","doi-asserted-by":"crossref","first-page":"1342","DOI":"10.1109\/TVLSI.2012.2208209","volume":"21","author":"L Pierce","year":"2013","unstructured":"Pierce L, Tragoudas S (2013) Enhanced secure architecture for joint action test group systems. IEEE Trans on Very Large Scale Integration (VLSI) Systems 21(7):1342\u20131345","journal-title":"IEEE Trans on Very Large Scale Integration (VLSI) Systems"},{"key":"5484_CR28","doi-asserted-by":"crossref","unstructured":"Rearick J, Volz A (2006) A case study of using IEEE P1687 (IJTAG) for high-speed serial I\/O characterization and testing. In: Proceedings of IEEE International Test Conference (ITC), paper 10.2","DOI":"10.1109\/TEST.2006.297620"},{"key":"5484_CR29","doi-asserted-by":"crossref","unstructured":"Rearick J, Eklow B, Posse K, Crouch A, Bennetts B (2005) IJTAG (Internal JTAG): A step toward a DFT standard. In: Proceedings of IEEE International Test Conference (ITC), paper, vol 32, p 4","DOI":"10.1109\/TEST.2005.1584044"},{"issue":"1","key":"5484_CR30","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/MDT.2010.9","volume":"27","author":"K Rosenfeld","year":"2010","unstructured":"Rosenfeld K, Karri R (2010) Attacks and defenses for JTAG. IEEE Design & Test Comput 27(1):36\u201347","journal-title":"IEEE Design & Test Comput"},{"key":"5484_CR31","doi-asserted-by":"crossref","unstructured":"Rosenfeld K, Karri R (2011) Security-aware SoC test access mechanisms. In: Proceedings of IEEE VLSI Test Symposium (VTS), pp 100\u2013104","DOI":"10.1109\/VTS.2011.5783765"},{"key":"5484_CR32","unstructured":"Sourgen L (1992) Security locks for integrated circuit US patent App. 5101121 A"},{"key":"5484_CR33","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4419-7563-8","volume-title":"On-chip instrumentation: design and debug for systems on chip","author":"N Stollon","year":"2011","unstructured":"Stollon N (2011) On-chip instrumentation: design and debug for systems on chip. Springer, US"},{"key":"5484_CR34","doi-asserted-by":"crossref","unstructured":"Tehranipoor M, Wang C (2011) Introduction to hardware security and trust. Springer","DOI":"10.1007\/978-1-4419-8080-9"},{"key":"5484_CR35","unstructured":"Yang B, Wu K, Karri R (2004) Scan based side channel attack on dedicated hardware implementations of data encryption standard. In: Proceedings of IEEE International Test Conference (ITC), pp 339\u2013344"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5484-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-014-5484-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5484-2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,16]],"date-time":"2019-08-16T08:42:28Z","timestamp":1565944948000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-014-5484-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10,18]]},"references-count":35,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2014,12]]}},"alternative-id":["5484"],"URL":"https:\/\/doi.org\/10.1007\/s10836-014-5484-2","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,10,18]]}}}