{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,14]],"date-time":"2026-02-14T07:21:38Z","timestamp":1771053698785,"version":"3.50.1"},"reference-count":29,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2014,10,28]],"date-time":"2014-10-28T00:00:00Z","timestamp":1414454400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1007\/s10836-014-5489-x","type":"journal-article","created":{"date-parts":[[2014,10,27]],"date-time":"2014-10-27T09:09:11Z","timestamp":1414400951000},"page":"739-749","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators"],"prefix":"10.1007","volume":"30","author":[{"given":"Reza","family":"Omidi Gosheblagh","sequence":"first","affiliation":[]},{"given":"Karim","family":"Mohammadi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,10,28]]},"reference":[{"issue":"4","key":"5489_CR1","doi-asserted-by":"crossref","first-page":"951","DOI":"10.1109\/TNS.2007.895550","volume":"54","author":"M-A Aguirre","year":"2007","unstructured":"Aguirre M-A, Tombs J-N, Muoz F (2007) Selective protection analysis using a SEU emulator: testing protocol and case study over the Leon2 processor. IEEE Trans Nucl Sci 54(4):951\u2013956","journal-title":"IEEE Trans Nucl Sci"},{"key":"5489_CR2","unstructured":"Albrecht C. IWLS 2005 benchmarks. Cadence Berkeley Labs, International Workshop for Logic Synthesis (IWLS), 8 June 2005"},{"issue":"4","key":"5489_CR3","doi-asserted-by":"crossref","first-page":"2129","DOI":"10.1109\/TNS.2010.2043855","volume":"57","author":"M Alderighi","year":"2010","unstructured":"Alderighi M, Casini F, D\u2019Angelo S, Liu SF, Sorrenti G, Reviriego P (2010) Experimental validation of fault injection analyses by the FLIPPER tool. IEEE Trans Nucl Sci 57(4):2129\u201334","journal-title":"IEEE Trans Nucl Sci"},{"issue":"4","key":"5489_CR4","doi-asserted-by":"crossref","first-page":"2103","DOI":"10.1109\/TNS.2009.2015880","volume":"56","author":"M Alderighi","year":"2009","unstructured":"Alderighi M, Casini F, Citterio M (2009) Using FLIPPER to predict proton irradiation results for Virtex 2 devices: acase study. IEEE Trans Nucl Sci 56(4):2103\u20132110","journal-title":"IEEE Trans Nucl Sci"},{"key":"5489_CR5","doi-asserted-by":"crossref","first-page":"1468","DOI":"10.1109\/TIM.2003.817144","volume":"52","author":"L Antoni","year":"2003","unstructured":"Antoni L, Leveugle R, Feher B (2003) Using run-time reconfiguration for fault injection applications. IEEE Trans Instrum Meas 52:1468\u201373","journal-title":"IEEE Trans Instrum Meas"},{"key":"5489_CR6","unstructured":"Carmichael C, Tseng CW (2009) Correcting single-event upsets in Virtex-4 FPGA configuration memory. Application note: XAPP1088"},{"key":"5489_CR7","doi-asserted-by":"crossref","first-page":"252","DOI":"10.1109\/TNS.2006.889115","volume":"54","author":"LO Celia","year":"2007","unstructured":"Celia LO, Mario GV, Marta PG, Luis E (2007) Autonomous fault emulation: a new FPGA-based acceleration system for hardness evaluation. IEEE Trans Nucl Sci 54:252\u201361","journal-title":"IEEE Trans Nucl Sci"},{"key":"5489_CR8","unstructured":"Chapman K (2010) SEU strategies for Virtex-5 devices. Xilinx corporation application notes:XAPP864"},{"issue":"6","key":"5489_CR9","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/MDT.2009.135","volume":"26","author":"L Dongwoo","year":"2009","unstructured":"Dongwoo L, Jongwhoa N (2009) A novel simulation fault injection method for dependability analysis. IEEE Des Test Comput 26(6):50\u201361","journal-title":"IEEE Des Test Comput"},{"key":"5489_CR10","unstructured":"Dutton B, Ali M, Stroud C, Sunwoo J(2009) Embedded processor based fault injection and SEU emulation for FPGAs. In International conf on embedded systems and applications; July 13\u201316; Las Vegas, Nevada, USA: pp. 183\u20139"},{"issue":"5","key":"5489_CR11","doi-asserted-by":"crossref","first-page":"627","DOI":"10.1007\/s10836-011-5245-4","volume":"27","author":"G Foucard","year":"2011","unstructured":"Foucard G, Peronnard P, Velazco R (2011) Reliability limits of TMR implemented in a SRAM-based FPGA: heavy ion measures vs. fault injection predictions. J Electron Test 27(5):627\u2013633","journal-title":"J Electron Test"},{"key":"5489_CR12","unstructured":"Goloubeva O, Rebaudengo M, Sonza M, Violante M (2006) Software-implemented hardware fault tolerance. Springer"},{"key":"5489_CR13","unstructured":"Johnson E, Caffrey M, Graham P, Rollins N, Wirthlin M (2003) The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets. In: 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM), 9\u201311 April xNapa, California, USA. pp. 133\u2013142"},{"key":"5489_CR14","doi-asserted-by":"crossref","first-page":"2147","DOI":"10.1109\/TNS.2003.821791","volume":"50","author":"E Johnson","year":"2003","unstructured":"Johnson E, Caffrey M, Graham P, Rollins N, Wirthlin M (2003) Accelerator validation of an FPGA SEU simulator. IEEE Trans Nucl Sci 50:2147\u201357","journal-title":"IEEE Trans Nucl Sci"},{"key":"5489_CR15","doi-asserted-by":"crossref","unstructured":"Kanamaru A, Kawai H, Yamaguchi Y (2009) Tile-based fault tolerant approach using partial reconfiguration reconfigurable computing: architectures, tools and applications. Lect Notes Comput Sci: Springer, Berlin, Heidelberg. p. 293\u2013299.","DOI":"10.1007\/978-3-642-00641-8_31"},{"key":"5489_CR16","doi-asserted-by":"crossref","first-page":"1724","DOI":"10.1016\/j.microrel.2008.06.003","volume":"48","author":"PM-H Lee","year":"2008","unstructured":"Lee PM-H, Sedaghat R (2008) FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration. Microelectron Reliab 48:1724\u201333","journal-title":"Microelectron Reliab"},{"key":"5489_CR17","doi-asserted-by":"crossref","first-page":"2562","DOI":"10.1109\/TNS.2012.2211617","volume":"59","author":"U Legat","year":"2012","unstructured":"Legat U, Biasizzo A, Novak F (2012) SEU recovery mechanism for SRAM-based FPGAs. IEEE Trans Nucl Sci 59:2562\u201371","journal-title":"IEEE Trans Nucl Sci"},{"key":"5489_CR18","volume-title":"A signature-based approach to formal logic verification","author":"J Mohnke","year":"1999","unstructured":"Mohnke J (1999) A signature-based approach to formal logic verification. Appendix: Benchmark Descriptions, Verteidigt"},{"issue":"5","key":"5489_CR19","first-page":"627","volume":"27","author":"M Portela-Garcia","year":"2012","unstructured":"Portela-Garcia M, Lindoso A, Entrena L (2012) Evaluating the effectiveness of a software-based technique under SEEs using FPGA-based fault injection approach. J Electron Test 27(5):627\u2013633","journal-title":"J Electron Test"},{"key":"5489_CR20","doi-asserted-by":"crossref","first-page":"3380","DOI":"10.1109\/TIM.2009.2025469","volume":"58","author":"HM Quinn","year":"2009","unstructured":"Quinn HM, Graham PS, Wirthlin MJ, Pratt B, Morgan KS, Caffrey MP, Krone JB (2009) A test methodology for determining space readiness of Xilinx SRAM-Based FPGA devices and designs. IEEE Trans Instrum Meas 58:3380\u201395","journal-title":"IEEE Trans Instrum Meas"},{"key":"5489_CR21","unstructured":"Schirrmann S (2011) User manual for Zefant-nanov4. Simple solutions corp"},{"key":"5489_CR22","unstructured":"Schumacher P (2012) SEU emulation environment. Xilinx whit paper: WP414 April 9"},{"issue":"1","key":"5489_CR23","doi-asserted-by":"crossref","first-page":"214","DOI":"10.1109\/TNS.2008.2010320","volume":"56","author":"RL Shuler","year":"2009","unstructured":"Shuler RL, Bhuva BL, O\u2019Neill PM (2009) Comparison of dual-rail and TMR logic cost effectiveness and suitability for FPGAs with reconfigurable SEU tolerance. IEEE Trans Nucl Sci 56(1):214\u201319","journal-title":"IEEE Trans Nucl Sci"},{"issue":"6","key":"5489_CR24","doi-asserted-by":"crossref","first-page":"732","DOI":"10.1109\/TC.2006.82","volume":"55","author":"L Sterpone","year":"2006","unstructured":"Sterpone L, Violante M (2006) A new reliability-oriented place and route algorithm for SRAM-based FPGAs. IEEE Trans Comput 55(6):732\u2013744","journal-title":"IEEE Trans Comput"},{"key":"5489_CR25","doi-asserted-by":"crossref","first-page":"732","DOI":"10.1109\/TC.2006.82","volume":"55","author":"L Sterpone","year":"2006","unstructured":"Sterpone L, Violante M (2006) A new reliability-oriented place and route algorithm for SRAM-based FPGAs. IEEE Trans Comput 55:732\u201344","journal-title":"IEEE Trans Comput"},{"key":"5489_CR26","unstructured":"Tombs J, Aguirre M-A (2004) FT-UNSHADES Tool Eur Space Agency Microelectron Day"},{"key":"5489_CR27","doi-asserted-by":"crossref","first-page":"3354","DOI":"10.1109\/TNS.2004.839516","volume":"51","author":"M Violante","year":"2004","unstructured":"Violante M, Sterpone L, Ceschia M, Bortolato D, Bernardi P, Reorda MS, Paccagnella A (2004) Simulation-based analysis of SEU effects in SRAM-based FPGAs. IEEE Trans Nucl Sci 51:3354\u20139","journal-title":"IEEE Trans Nucl Sci"},{"key":"5489_CR28","unstructured":"Xilinx C. PlanAhead user guide. Xilinx product documents: UG632, 2009."},{"key":"5489_CR29","unstructured":"Xilinx C (2009) Virtex-4 FPGA configuration user guide. Xilinx corporation document: UG071"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5489-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-014-5489-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-014-5489-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,16]],"date-time":"2019-08-16T17:28:22Z","timestamp":1565976502000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-014-5489-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10,28]]},"references-count":29,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2014,12]]}},"alternative-id":["5489"],"URL":"https:\/\/doi.org\/10.1007\/s10836-014-5489-x","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,10,28]]}}}