{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T07:35:10Z","timestamp":1648712110150},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2016,9,5]],"date-time":"2016-09-05T00:00:00Z","timestamp":1473033600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1007\/s10836-016-5610-4","type":"journal-article","created":{"date-parts":[[2016,9,5]],"date-time":"2016-09-05T03:41:30Z","timestamp":1473046890000},"page":"511-529","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Optimization of Test Wrapper for TSV Based 3D SOCs"],"prefix":"10.1007","volume":"32","author":[{"given":"Surajit Kumar","family":"Roy","sequence":"first","affiliation":[]},{"given":"Chandan","family":"Giri","sequence":"additional","affiliation":[]},{"given":"Hafizur","family":"Rahaman","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,9,5]]},"reference":[{"key":"5610_CR1","doi-asserted-by":"crossref","unstructured":"Banerjee K, Souri SJ, Kapur P, Saraswat KC (2001) 3-D ICS: a novel chip design for improving deep sub-micrometer interconnect performance and system-on-chip integration. In: Proc. of the IEEE, vol 89, pp 602\u2013633","DOI":"10.1109\/5.929647"},{"key":"5610_CR2","doi-asserted-by":"crossref","unstructured":"Cheng Y, Zhang L, Han Y, Li X (2013) TSV Minimization for circuit partitioned 3D SoC test wrapper design. In: Journal of computer science and technology, vol 28, pp 119\u2013128","DOI":"10.1007\/s11390-013-1316-6"},{"key":"5610_CR3","doi-asserted-by":"crossref","unstructured":"Davis WR, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule A, Steer M, Franzon P (2005) Demystifying 3D ICs: the pros and cons of going vertical. In: IEEE design and test of computers, vol 22, pp 498\u2013510","DOI":"10.1109\/MDT.2005.136"},{"key":"5610_CR4","doi-asserted-by":"crossref","unstructured":"Goel SK, Marinissen EJ (2003) SOC test architecture design for efficient utilization of test bandwidth. In: ACM Trans. design automation of electronic systems, vol 8, pp 399\u2013429","DOI":"10.1145\/944027.944029"},{"key":"5610_CR5","doi-asserted-by":"crossref","unstructured":"Giri C, Roy SK, Banerjee B, Rahaman H (2009) Scan chain design targeting dual power and delay optimization for 3D integrated circuits. In: Proc.of IEEE Intl. Conf. on advances in computing, control, and telecommunication technologies India, pp 845\u2013849","DOI":"10.1109\/ACT.2009.214"},{"key":"5610_CR6","doi-asserted-by":"crossref","unstructured":"Giri C, Sarkar S, Chattopadhyaya S (2007) A Genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. In: Proc. of IEEE Intl. Conf. on IFIP VLSI-SOC, pp 320\u2013323","DOI":"10.1109\/VLSISOC.2007.4402522"},{"key":"5610_CR7","doi-asserted-by":"crossref","unstructured":"Huang Y, Reddy SM, Cheng W-T, Reuter P, Mukherjee N, Tsai C-C, Samman O, Zaidan Y (2002) Optimal core Wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm. In: Proc. of international test conference, pp 74\u201382","DOI":"10.1109\/TEST.2002.1041747"},{"key":"5610_CR8","doi-asserted-by":"crossref","unstructured":"Iyengar V, Chakrabarty K, Marinissen EJ (2002) Test wrapper and test access mechanism co-optimization for system-on-chip. In: Journal of electronic testing: theory and applications(JETTA), vol 18, pp 213\u2013230","DOI":"10.1023\/A:1014916913577"},{"key":"5610_CR9","unstructured":"(2005) IEEE Std. 1500: IEEE standard testability method for embedded core-based integrated circuits, IEEE press"},{"key":"5610_CR10","doi-asserted-by":"crossref","unstructured":"Jiang L, Huang L, Xu Q (2009) Test architecture design and optimization for three-dimensional SOCs. In: Proc. of design,automation and test in Europe, pp 220\u2013225","DOI":"10.1109\/DATE.2009.5090661"},{"key":"5610_CR11","unstructured":"Jiang L, Xu Q, Chakrabarty K, Mak T (2009) Layout driven test-architecture design and optimization for 3D SoCs under prebond test-pin-count constraint. In: IEEE international conference on computer design, pp 191\u2013196"},{"key":"5610_CR12","doi-asserted-by":"crossref","unstructured":"Marinissen EJ, Verbree J, Konijnenburg M (2010) A structured and scalable test access architecture for TSV-based 3D stacked ICs. In: Proc VLSI test symposium, pp 269\u2013274","DOI":"10.1109\/VTS.2010.5469556"},{"key":"5610_CR13","doi-asserted-by":"crossref","unstructured":"Noia B, Chakrabarty K (2009) Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. In: Proc IEEE international conference on computer design, pp 70\u201377","DOI":"10.1109\/ICCD.2009.5413172"},{"key":"5610_CR14","doi-asserted-by":"crossref","unstructured":"Noia B, Chakrabarty K, Marinissen EJ (2010) Optimization methods for post-bond die-internal\/external testing in 3D stacked ICs. In: Proc. of international test conference, pp 1\u20139","DOI":"10.1109\/TEST.2010.5699219"},{"key":"5610_CR15","doi-asserted-by":"crossref","unstructured":"Noia B, Chakrabarty K, Xie Y (2011) Test-Wrapper Optimization for embedded cores in through-silicon-via based three-dimensional system on chips. In: IET computers and digital techniques, vol 5, pp 186\u2013197","DOI":"10.1049\/iet-cdt.2009.0111"},{"key":"5610_CR16","doi-asserted-by":"crossref","unstructured":"Puttaswamy K, Loh GH (2007) Thermal herding: microarchitecture techniques for controlling hotspots in high performance 3D integrated processors. In: IEEE High Performance computer architecture, pp 193\u2013204","DOI":"10.1109\/HPCA.2007.346197"},{"key":"5610_CR17","doi-asserted-by":"crossref","unstructured":"Roy SK, Ghosh S, Rahaman H, Giri C (2010) Test wrapper design for 3D system-on-chip using optimized number of TSVs. In: Proc. of IEEE Intl. symposium on electronic system design, pp 197\u2013202","DOI":"10.1109\/ISED.2010.45"},{"key":"5610_CR18","doi-asserted-by":"crossref","unstructured":"Roy SK, Ghosh S, Rahaman H, Giri C (2011) Optimization of test wrapper for TSV based 3D SOCs. In: Proc. of IEEE Intl. symposium on electronic system design, pp 188\u2013193","DOI":"10.1109\/ISED.2011.26"},{"key":"5610_CR19","doi-asserted-by":"crossref","unstructured":"Wu X, Chen Y, Chakrabarty K, Xie Y (2008) Test Access mechanism optimization for core-based three-dimensional SOCs. In: IEEE international conference on computer design, pp 212\u2013218","DOI":"10.1109\/ICCD.2008.4751864"},{"key":"5610_CR20","doi-asserted-by":"crossref","unstructured":"Xie Y, Loh GH, Black B, Bernstein K (2006) Design space exploration for 3D architectures. In: ACM Journal of emerging technology and computer systems, vol 2, pp 63\u2013103","DOI":"10.1145\/1148015.1148016"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-016-5610-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-016-5610-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-016-5610-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-016-5610-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,13]],"date-time":"2019-09-13T06:00:18Z","timestamp":1568354418000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-016-5610-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9,5]]},"references-count":20,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2016,10]]}},"alternative-id":["5610"],"URL":"https:\/\/doi.org\/10.1007\/s10836-016-5610-4","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,9,5]]}}}