{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:40:39Z","timestamp":1740123639897,"version":"3.37.3"},"reference-count":55,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2017,6,5]],"date-time":"2017-06-05T00:00:00Z","timestamp":1496620800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2017,8]]},"DOI":"10.1007\/s10836-017-5666-9","type":"journal-article","created":{"date-parts":[[2017,6,5]],"date-time":"2017-06-05T00:38:47Z","timestamp":1496623127000},"page":"501-513","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip"],"prefix":"10.1007","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2209-9967","authenticated-orcid":false,"given":"Babak","family":"Aghaei","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmad","family":"Khademzadeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Midia","family":"Reshadi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kambiz","family":"Badie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,6,5]]},"reference":[{"key":"5666_CR1","unstructured":"Agarwal A, Iskander C, Shankar R (2009) Survey of network on chip (NoC) architectures & contributions. Journal of Engineering, Computing and Architecture 3(1):21\u201327"},{"key":"5666_CR2","doi-asserted-by":"crossref","unstructured":"Aghaei B, Babaei S (2009) The new test wrapper design for core testing in packet-switched micro-network on chip. In: Proceedings 2nd IEEE International Conference on Power Electronics and Intelligent Transportation System, pp 19-20","DOI":"10.1109\/PEITS.2009.5406770"},{"key":"5666_CR3","doi-asserted-by":"crossref","unstructured":"Aghaei B, Khademzadeh A, Reshadi M, Badie K (2017) Link testing: a survey of current trends in network on chip. J Electron Test 33(2):209\u2013225","DOI":"10.1007\/s10836-017-5646-0"},{"key":"5666_CR4","doi-asserted-by":"crossref","unstructured":"Alaghi A, Karimi N, Sedghi M, Navabi Z (2007) Online NoC switch fault detection and diagnosis using a high level fault model. In: Proc. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), pp 21-29","DOI":"10.1109\/DFT.2007.55"},{"key":"5666_CR5","doi-asserted-by":"crossref","unstructured":"Alamian SS, Fallahzadeh R, Hessabi S, Alirezaie J (2013) A novel test strategy and fault-tolerant routing algorithm for NoC routers. In: Proc. 17th IEEE CSI international Symposium on Computer Architecture & Digital Systems (CADS), pp 133-136","DOI":"10.1109\/CADS.2013.6714252"},{"key":"5666_CR6","doi-asserted-by":"crossref","unstructured":"Amory AM, Bri\u00e3o E, Cota \u00c9, Lubaszewski M, Moraes FG (2005) A scalable test strategy for network-on-chip routers. In: Proc. IEEE International Test Conference (ITC), pp 9-599","DOI":"10.1109\/TEST.2005.1584020"},{"issue":"3","key":"5666_CR7","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1049\/iet-cdt:20060152","volume":"1","author":"AM Amory","year":"2007","unstructured":"Amory AM, Goossens K, Marinissen EJ, Lubaszewski M, Moraes F (2007) Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. Comp Digit Tech, IET 1(3):197\u2013206","journal-title":"Comp Digit Tech, IET"},{"key":"5666_CR8","unstructured":"Babaei S, Mansouri M, Aghaei B, Khadem-Zadeh A (2011) Online-structural testing of routers in network on chip. World Appl Sci J 14(9):1374\u20131383"},{"issue":"1","key":"5666_CR9","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. Computer 35(1):70\u201378","journal-title":"Computer"},{"key":"5666_CR10","doi-asserted-by":"crossref","unstructured":"Bhowmik B, Deka JK, Biswas S (2015) An odd-even model for diagnosis of shorts on NoC interconnects. In: Proc. Annual IEEE India Conference (INDICON), pp 1-6","DOI":"10.1109\/INDICON.2015.7443393"},{"key":"5666_CR11","doi-asserted-by":"crossref","unstructured":"Bhowmik B, Biswas S, Deka JK (2016) Impact of NoC interconnect shorts on performance metrics. In: Proc. 22nd IEEE National Conference on Communication (NCC), pp 16","DOI":"10.1109\/NCC.2016.7561197"},{"key":"5666_CR12","doi-asserted-by":"crossref","unstructured":"Bhowmik B, Deka JK, Biswas S (2016) An on-line test solution for addressing interconnect shorts in on-chip networks. In: Proc. 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pp 9-12","DOI":"10.1109\/IOLTS.2016.7604660"},{"key":"5666_CR13","doi-asserted-by":"crossref","unstructured":"Borkar S (2007) Thousand core chips: a technology perspective. In: Proceedings 44th ACM Annual Design Automation Conference, pp 746-749","DOI":"10.1145\/1278480.1278667"},{"key":"5666_CR14","unstructured":"Chen G (2013) SPAcENoCs: a scalable platform for FPGA accelerated emulator of NoCs. Texas A&M University"},{"key":"5666_CR15","first-page":"48109","volume":"1001","author":"AC Cheng","year":"2002","unstructured":"Cheng AC (2002) Comprehensive study on designing memory BIST: algorithms, implementations and trade-offs. Ann Arbor 1001:48109\u201342122","journal-title":"Ann Arbor"},{"key":"5666_CR16","doi-asserted-by":"crossref","unstructured":"Concatto C, Almeida P, Kastensmidt F, Cota E, Lubaszewski M, Herve M (2009) Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults. In: Proc. 15th IEEE International On-Line Testing Symposium, pp 61-66","DOI":"10.1109\/IOLTS.2009.5195984"},{"issue":"4","key":"5666_CR17","doi-asserted-by":"crossref","first-page":"471","DOI":"10.1145\/1027084.1027088","volume":"9","author":"\u00c9 Cota","year":"2004","unstructured":"Cota \u00c9, Carro L, Lubaszewski M (2004) Reusing an on-chip network for the test of core-based systems. ACM Trans Des Autom Electron Syst 9(4):471\u2013499","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"5666_CR18","doi-asserted-by":"crossref","unstructured":"Cota E, Kastensmidt FL, Cassel M, Herv\u00e9 M, Almeida P, Meirelles P, Amory A, Lubaszewski M (2008) A high-fault-coverage approach for the test of data, control, and handshake interconnects in mesh networks-on-chip. IEEE Trans Comput 57(9):1202\u20131215","DOI":"10.1109\/TC.2008.62"},{"key":"5666_CR19","doi-asserted-by":"crossref","unstructured":"Cota \u00c9, de Morais AA, Lubaszewski MS (2012) Test and diagnosis of routers. In: Reliability, Availability and Serviceability of Networks-on-Chip. Springer, pp 115\u2013132","DOI":"10.1007\/978-1-4614-0791-1_6"},{"key":"5666_CR20","doi-asserted-by":"crossref","unstructured":"Cuviello M, Dey S, Bai X, Zhao Y (1999) Fault modeling and simulation for crosstalk in system-on-chip interconnects. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design, pp 297\u2013303","DOI":"10.1109\/ICCAD.1999.810665"},{"key":"5666_CR21","doi-asserted-by":"crossref","unstructured":"Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceeding IEEE Design Automation Conference, pp 684\u2013689","DOI":"10.1109\/DAC.2001.935594"},{"key":"5666_CR22","unstructured":"Dally WJ, Towles BP (2004) Principles and practices of interconnection networks. Elsevier, Amsterdam (Imprint: Morgan Kaufmann)"},{"key":"5666_CR23","doi-asserted-by":"crossref","unstructured":"Fick D, DeOrio A, Hu J, Bertacco V, Blaauw D, Sylvester D (2009) Vicis: a reliable network for unreliable silicon. In: Proceeding 46th ACM Annual Design Automation Conference, pp 812-817","DOI":"10.1145\/1629911.1630119"},{"key":"5666_CR24","doi-asserted-by":"crossref","unstructured":"Ghofrani A, Parikh R, Shamshiri S, DeOrio A, Cheng K-T, Bertacco V (2012) Comprehensive online defect diagnosis in on-chip networks. In: Proc. 30th IEEE VLSI Test Symposium, pp 44\u201349","DOI":"10.1109\/VTS.2012.6231078"},{"issue":"5","key":"5666_CR25","doi-asserted-by":"crossref","first-page":"414","DOI":"10.1109\/MDT.2005.99","volume":"22","author":"K Goossens","year":"2005","unstructured":"Goossens K, Dielissen J, Radulescu A (2005) \u00c6thereal network on chip: concepts, architectures, and implementations. IEEE Design Test Comput 22(5):414\u2013421","journal-title":"IEEE Design Test Comput"},{"key":"5666_CR26","doi-asserted-by":"crossref","unstructured":"Grecu C, Pande P, Ivanov A, Saleh R (2006) BIST for network-on-chip interconnect infrastructures. In: Proc. 24th IEEE VLSI Test Symposium, pp 30-35","DOI":"10.1109\/VTS.2006.22"},{"key":"5666_CR27","doi-asserted-by":"crossref","unstructured":"Han T, Choi I, Oh H, Kang S (2014) A scalable and parallel test access strategy for NoC-based multicore system. In: 23rd IEEE Asian Test Symposium (ATS), pp 81-86","DOI":"10.1109\/ATS.2014.26"},{"key":"5666_CR28","doi-asserted-by":"crossref","unstructured":"Hassan A, Rajski J, Agarwal VK (1988) Testing and diagnosis of interconnects using boundary scan architecture. In: Proceeding IEEE International Test Conference, New Frontiers in Testing, pp 126\u2013137","DOI":"10.1109\/TEST.1988.207790"},{"key":"5666_CR29","doi-asserted-by":"crossref","unstructured":"Henkel J, Wolf W, Chakradhar S (2004) On-chip networks: a scalable, communication-centric embedded system design paradigm. In: Proceeding 17th IEEE International Conference on VLSI Design, pp 845-851","DOI":"10.1109\/ICVD.2004.1261037"},{"key":"5666_CR30","doi-asserted-by":"crossref","unstructured":"Herve M, Cota E, Kastensmidt FL, Lubaszewski M (2009) Diagnosis of interconnect shorts in mesh NoCs. In: Proc. 3rd ACM\/IEEE International Symposium on Networks-on-Chip, pp 256-265","DOI":"10.1109\/NOCS.2009.5071475"},{"key":"5666_CR31","doi-asserted-by":"crossref","unstructured":"Herv\u00e9 M, Almeida P, Kastensmidt FL, Cota E, Lubaszewski M (2010) Concurrent test of network-on-chip interconnects and routers. In: Proc. 11th Latin American Test Workshop","DOI":"10.1109\/LATW.2010.5550355"},{"key":"5666_CR32","doi-asserted-by":"crossref","unstructured":"Holsmark R, Kumar S (2005) Design issues and performance evaluation of mesh NoC with regions. In: Proc IEEE NORCHIP, pp 40\u201343","DOI":"10.1109\/NORCHP.2005.1596984"},{"key":"5666_CR33","doi-asserted-by":"crossref","unstructured":"Hosseinabady M, Dalirsani A, Navabi Z (2007) Using the inter-and intra-switch regularity in NoC switch testing. In: Proc. European Conference on Design, Automation and Test and EDA Consortium, pp 361\u2013366","DOI":"10.1109\/DATE.2007.364618"},{"key":"5666_CR34","doi-asserted-by":"crossref","unstructured":"Kakoee MR, Bertacco V, Benini L (2011) A distributed and topology-agnostic approach for on-line NoC testing. In: Proc. Fifth ACM\/IEEE International Symposium on Networks-on-Chip, pp 113\u2013120","DOI":"10.1145\/1999946.1999965"},{"issue":"3","key":"5666_CR35","doi-asserted-by":"crossref","first-page":"703","DOI":"10.1109\/TC.2013.202","volume":"63","author":"MR Kakoee","year":"2014","unstructured":"Kakoee MR, Bertacco V, Benini L (2014) At-speed distributed functional testing to detect logic and delay faults in NoCs. IEEE Trans Comput 63(3):703\u2013717","journal-title":"IEEE Trans Comput"},{"issue":"4","key":"5666_CR36","doi-asserted-by":"crossref","first-page":"358","DOI":"10.1109\/T-C.1974.223950","volume":"100","author":"WH Kautz","year":"1974","unstructured":"Kautz WH (1974) Testing for faults in wiring networks. IEEE Trans Comput 100(4):358\u2013363","journal-title":"IEEE Trans Comput"},{"key":"5666_CR37","unstructured":"Kim J-S, Hwang M-S, Roh S, Lee J-Y, Lee K, Lee S-J, Yoo H-J (2004) On-chip network based embedded core testing. In: Proceeding IEEE International SoC Conference, pp 223\u2013226"},{"key":"5666_CR38","doi-asserted-by":"crossref","unstructured":"Krstic A, Cheng K-T (1998) Delay fault testing for VLSI circuits, Springer Science & Business Media","DOI":"10.1007\/978-1-4615-5597-1"},{"key":"5666_CR39","unstructured":"Lien J-C, Breuer MA (1991) Maximal diagnosis for wiring networks. In: Proceeding International Test Conference, pp 96\u2013105"},{"issue":"1","key":"5666_CR40","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1016\/j.vlsi.2004.03.003","volume":"38","author":"F Moraes","year":"2004","unstructured":"Moraes F, Calazans N, Mello A, M\u00f6ller L, Ost L (2004) HERMES: an infrastructure for low area overhead packet-switching networks on chip. VLSI J Integ 38(1):69\u201393","journal-title":"VLSI J Integ"},{"key":"5666_CR41","unstructured":"Nazari M, Zolfy Lighvan M, Daie Koozekonani Z, Sadeghi A (2016) A novel HW\/SW based NoC router self-testing methodology. arXiv preprint arXiv:160904569"},{"key":"5666_CR42","unstructured":"Nazarian G (2008) On-line testing of routers in networks-on-chip. PhD thesis, Delft University of Technology"},{"key":"5666_CR43","doi-asserted-by":"crossref","unstructured":"Peters\u00e9n K, \u00d6berg J (2007) Toward a scalable test methodology for 2D\u2013mesh network-on-chips. In: Proc. European Conference on Design, Automation and Test and EDA Consortium, pp 367\u2013372","DOI":"10.1109\/DATE.2007.364619"},{"key":"5666_CR44","unstructured":"Spartan XD (2013) 3E FPGA family data sheet. DS312 (July 19)"},{"key":"5666_CR45","doi-asserted-by":"crossref","unstructured":"Strano A, G\u00f3mez C, Ludovici D, Favalli M, G\u00f3mez ME, Bertozzi D (2011) Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In: Proc. IEEE Design, Automation & Test in Europe, pp 1\u20136","DOI":"10.1109\/DATE.2011.5763109"},{"key":"5666_CR46","unstructured":"Stroud CE (2002) A Designer's guide to built-in self-test. Springer Science & Business Media"},{"key":"5666_CR47","unstructured":"Ubar R, Raik J (2003) Testing strategies for networks on chip. In: Networks on Chip. Springer, pp 131\u2013152"},{"issue":"9","key":"5666_CR48","doi-asserted-by":"crossref","first-page":"74","DOI":"10.1109\/MCOM.2003.1232240","volume":"41","author":"B Vermeulen","year":"2003","unstructured":"Vermeulen B, Dielissen J, Goossens K, Ciordas C (2003) Bringing communication networks on a chip: test and verification implications. IEEE Commun Mag 41(9):74\u201381","journal-title":"IEEE Commun Mag"},{"issue":"2","key":"5666_CR49","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1145\/2821506","volume":"21","author":"D Xiang","year":"2016","unstructured":"Xiang D, Shen K (2016) A new unicast-based multicast scheme for network-on-chip router and interconnect testing. ACM Trans Des Autom Electron Syst 21(2):24","journal-title":"ACM Trans Des Autom Electron Syst"},{"issue":"1","key":"5666_CR50","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1109\/TCAD.2010.2066070","volume":"30","author":"D Xiang","year":"2011","unstructured":"Xiang D, Zhang Y (2011) Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme. IEEE Trans Compr-Aided Design Integ Circ Syst 30(1):135\u2013147","journal-title":"IEEE Trans Compr-Aided Design Integ Circ Syst"},{"issue":"9","key":"5666_CR51","doi-asserted-by":"crossref","first-page":"2767","DOI":"10.1109\/TC.2015.2493548","volume":"65","author":"D Xiang","year":"2016","unstructured":"Xiang D, Chakrabarty K, Fujiwara H (2016) Multicast-based testing and thermal-aware test scheduling for 3D ICs with a stacked network-on-chip. IEEE Trans Comput 65(9):2767\u20132779","journal-title":"IEEE Trans Comput"},{"key":"5666_CR52","unstructured":"Xilinx I (2014) Design Suite version:14.4"},{"issue":"5","key":"5666_CR53","doi-asserted-by":"crossref","first-page":"247","DOI":"10.14257\/ijca.2013.6.5.23","volume":"6","author":"Z Ying","year":"2013","unstructured":"Ying Z, Ning W, Fen G, Xin C, Lei Z (2013) Novel Core test wrapper design supporting multi-mode testing of NoC-based SoC. Inter J Control Autom 6(5):247\u2013262","journal-title":"Inter J Control Autom"},{"key":"5666_CR54","doi-asserted-by":"crossref","unstructured":"Zeferino CA, Kreutz ME, Carro L, Susin AA (2002) A study on communication issues for systems-on-chip. In: Proc. 15th IEEE Symposium on Integrated Circuits and Systems Design, pp 121-126","DOI":"10.1109\/SBCCI.2002.1137647"},{"key":"5666_CR55","doi-asserted-by":"crossref","unstructured":"Zeferino CA, Kreutz ME, Susin AA (2004) RASoC: a router soft-core for networks-on-chip. In: Proc. IEEE Design,, Automation and Test in Europe Conference, pp 198-203","DOI":"10.1109\/DATE.2004.1269230"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-017-5666-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-017-5666-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-017-5666-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,25]],"date-time":"2019-09-25T12:01:23Z","timestamp":1569412883000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-017-5666-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6,5]]},"references-count":55,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,8]]}},"alternative-id":["5666"],"URL":"https:\/\/doi.org\/10.1007\/s10836-017-5666-9","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2017,6,5]]}}}