{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:39:06Z","timestamp":1740123546445,"version":"3.37.3"},"reference-count":45,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T00:00:00Z","timestamp":1519344000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1007\/s10836-018-5714-0","type":"journal-article","created":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T01:50:31Z","timestamp":1519350631000},"page":"123-134","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Detectability Challenges of Bridge Defects in FinFET Based Logic Cells"],"prefix":"10.1007","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9939-0974","authenticated-orcid":false,"given":"Freddy","family":"Forero","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Marc","family":"Galliere","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michel","family":"Renovell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor","family":"Champac","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,2,23]]},"reference":[{"key":"5714_CR1","unstructured":"Abercrombie D, Ferguson J (2010) The (desing) house always wins-how dfm improves the odds of tapeout success. http:\/\/chipdesignmag.com\/display.php?articleId=4616 . Online; Accessed 20 Jan 2018"},{"issue":"5","key":"5714_CR2","doi-asserted-by":"publisher","first-page":"751","DOI":"10.1109\/TVLSI.2010.2040094","volume":"19","author":"M Alioto","year":"2011","unstructured":"Alioto M (2011) Comparative evaluation of layout density in 3t, 4t, and mt finfet standard cells. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19(5):751\u2013762. https:\/\/doi.org\/10.1109\/TVLSI.2010.2040094","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"5714_CR3","unstructured":"Predictive technology model. ptm.asu.edu . Online; Accessed 20 Jan 2018"},{"key":"5714_CR4","unstructured":"Baars P, Geiss EP (2012) Integrated circuits including copper local interconnects and methods for the manufacture thereof. US Patent App. 13\/361,644"},{"key":"5714_CR5","volume-title":"Wafer-level testing and test during burn-in for integrated circuits","author":"S Bahukudumbi","year":"2010","unstructured":"Bahukudumbi S, Chakrabarty K (2010) Wafer-level testing and test during burn-in for integrated circuits. Artech House, Norwood"},{"issue":"1","key":"5714_CR6","doi-asserted-by":"publisher","first-page":"182","DOI":"10.1109\/TNANO.2011.2169807","volume":"11","author":"A Bhoj","year":"2012","unstructured":"Bhoj A, Simsir MO, Jha NK (2012) Fault models for logic circuits in the multigate era. IEEE Trans Nanotechnol 11(1):182\u2013193","journal-title":"IEEE Trans Nanotechnol"},{"key":"5714_CR7","unstructured":"Bsim-cmg model. http:\/\/bsim.berkeley.edu\/models\/bsimcmg . Online; Accessed 20 Jan 2018"},{"key":"5714_CR8","doi-asserted-by":"crossref","unstructured":"Chiang KY, Ho YH, Chen YW, Pan CS, Li JCM (2015) Fault simulation and test pattern generation for cross-gate defects in finfet circuits. In: Proceedings of the 2015 IEEE 24th asian test symposium (ATS). IEEE, pp 181\u2013186","DOI":"10.1109\/ATS.2015.38"},{"key":"5714_CR9","doi-asserted-by":"publisher","unstructured":"Cui T, Xie Q, Wang Y, Nazarian S, Pedram M (2014) 7nm finfet standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes. In: Proceedings of the international green computing conference, pp 1\u20137. https:\/\/doi.org\/10.1109\/IGCC.2014.7039170","DOI":"10.1109\/IGCC.2014.7039170"},{"key":"5714_CR10","doi-asserted-by":"publisher","unstructured":"Du L, Zhao H, Yang W, Yang R, Chen L, Yu S, Mao G, Wang Q, Lin Y, Ding S, Chen Z (2015) Optimization of sti oxide recess uniformity for finfet beyond 20nm. In: Proceedings of the 2015 China semiconductor technology international conference, pp 1\u20134. https:\/\/doi.org\/10.1109\/CSTIC.2015.7153433","DOI":"10.1109\/CSTIC.2015.7153433"},{"key":"5714_CR11","doi-asserted-by":"publisher","unstructured":"Duarte JP, Khandelwal S, Medury A, Hu C, Kushwaha P, Agarwal H, Dasgupta A, Chauhan YS (2015) Bsim-cmg: standard finfet compact model for advanced circuit design. In: Proceedings of the ESSCIRC conference 2015 - 41st European solid-state circuits conference (ESSCIRC), pp 196\u2013201. https:\/\/doi.org\/10.1109\/ESSCIRC.2015.7313862","DOI":"10.1109\/ESSCIRC.2015.7313862"},{"issue":"2","key":"5714_CR12","doi-asserted-by":"publisher","first-page":"327","DOI":"10.1109\/TCAD.2007.913382","volume":"27","author":"P Engelke","year":"2008","unstructured":"Engelke P, Polian I, Renovell M, Kundu S, Seshadri B, Becker B (2008) On detection of resistive bridging defects by low-temperature and low-voltage testing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(2):327\u2013338. https:\/\/doi.org\/10.1109\/TCAD.2007.913382","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"5714_CR13","doi-asserted-by":"crossref","unstructured":"Ferguson FJ, Shen JP (1988) Extraction and simulation of realistic cmos faults using inductive fault analysis. In: Proc. test conference, 1988. Proceedings. New frontiers in testing international. IEEE, pp 475\u2013484","DOI":"10.1109\/TEST.1988.207759"},{"key":"5714_CR14","doi-asserted-by":"publisher","unstructured":"Forero F, Galliere JM, Renovell M, Champac V (2017) Analysis of short defects in finfet based logic cells. In: Proceedings of the 2017 18th IEEE Latin American test symposium (LATS), pp 1\u20136. https:\/\/doi.org\/10.1109\/LATW.2017.7906755","DOI":"10.1109\/LATW.2017.7906755"},{"key":"5714_CR15","doi-asserted-by":"crossref","unstructured":"Harutyunyan G, Shoukourian S, Vardanian V, Zorian Y (2014) Extending fault periodicity table for testing faults in memories under 20nm. In: Proceedings of design & test symposium (EWDTS), 2014 East-West. IEEE, pp 1\u20134","DOI":"10.1109\/EWDTS.2014.7027088"},{"key":"5714_CR16","doi-asserted-by":"crossref","unstructured":"Harutyunyan G, Tshagharyan G, Vardanian V, Zorian Y (2014) Fault modeling and test algorithm creation strategy for finfet-based memories. In: Proceedings of the 2014 IEEE 32nd VLSI test symposium (VTS). IEEE, pp 1\u20136","DOI":"10.1109\/VTS.2014.6818747"},{"key":"5714_CR17","unstructured":"Itrs 2012 executive summary. http:\/\/www.itrs2.net . Online; Accessed 20 Jan 2018"},{"key":"5714_CR18","doi-asserted-by":"publisher","unstructured":"Joseph J, Patrikar R (2013) Impact of fin width and graded channel doping on the performance of 22nm SOI FinFET. In: VLSI design and test. Communications in computer and information science. Springer, Berlin, pp 153\u2013159. https:\/\/doi.org\/10.1007\/978-3-642-42024-5_19","DOI":"10.1007\/978-3-642-42024-5_19"},{"key":"5714_CR19","doi-asserted-by":"publisher","unstructured":"Karel A, Comte M, Galliere JM, Azais F, Renovell M (2016) Comparative study of bulk, fdsoi and finfet technologies in presence of a resistive short defect. In: Proceedings of the 2016 17th Latin-American test symposium (LATS), pp 129\u2013134. https:\/\/doi.org\/10.1109\/LATW.2016.7483352","DOI":"10.1109\/LATW.2016.7483352"},{"issue":"4","key":"5714_CR20","doi-asserted-by":"publisher","first-page":"515","DOI":"10.1007\/s10836-017-5674-9","volume":"33","author":"A Karel","year":"2017","unstructured":"Karel A, Comte M, Galliere JM, Azais F, Renovell M (2017) Resistive bridging defect detection in bulk, fdsoi and finfet technologies. J Electron Test 33(4):515\u2013527. https:\/\/doi.org\/10.1007\/s10836-017-5674-9","journal-title":"J Electron Test"},{"issue":"864","key":"5714_CR21","first-page":"725","volume":"13","author":"A Katoch","year":"2014","unstructured":"Katoch A, Adham SM, O\u2019connell CM (2014) Fault injection of finfet devices. US Patent App. 13 (864):725","journal-title":"US Patent App."},{"key":"5714_CR22","doi-asserted-by":"publisher","unstructured":"Kauerauf T, Branka A, Sorrentino G, Roussel P, Demuynck S, Croes K, Mercha K, B\u00f6mmels J, To\u030bkei Z, Groeseneken G (2013) Reliability of mol local interconnects. In: Proceedings of the 2013 IEEE international reliability physics symposium (IRPS), pp 2F.5.1\u20132F.5.5. https:\/\/doi.org\/10.1109\/IRPS.2013.6531970","DOI":"10.1109\/IRPS.2013.6531970"},{"key":"5714_CR23","doi-asserted-by":"publisher","unstructured":"Kedzierski J, Fried DM, Nowak EJ, Kanarsky T, Rankin JH, Hanafi H, Natzle W, Boyd D, Zhang Y, Roy RA et al (2001) High-performance symmetric-gate and cmos-compatible v\/sub t\/ asymmetric-gate finfet devices. In: Proceedings of the international electron devices meeting. Technical digest (Cat. No.01CH37224), pp 19.5.1\u201319.5.4. https:\/\/doi.org\/10.1109\/IEDM.2001.979530","DOI":"10.1109\/IEDM.2001.979530"},{"key":"5714_CR24","doi-asserted-by":"publisher","unstructured":"Kleeberger VB, Graeb H, Schlichtmann U (2013) Predicting future product performance: modeling and evaluation of standard cells in finfet technologies. In: Proceedings of the 2013 50th ACM\/EDAC\/IEEE design automation conference (DAC), pp 1\u20136. https:\/\/doi.org\/10.1145\/2463209.2488775","DOI":"10.1145\/2463209.2488775"},{"key":"5714_CR25","doi-asserted-by":"crossref","unstructured":"Liu Y, Xu Q (2012) On modeling faults in finfet logic circuits. In: 2012 IEEE international test conference. IEEE, pp 1\u20139","DOI":"10.1109\/TEST.2012.6401565"},{"key":"5714_CR26","doi-asserted-by":"publisher","unstructured":"Lu DD, Dunga MV, Lin CH, Niknejad AM, Hu C (2007) A multi-gate mosfet compact model featuring independent-gate operation. In: Proceedings of the 2007 IEEE international electron devices meeting, pp 565\u2013568. https:\/\/doi.org\/10.1109\/IEDM.2007.4419001","DOI":"10.1109\/IEDM.2007.4419001"},{"key":"5714_CR27","doi-asserted-by":"publisher","unstructured":"Mandava S, Chakravarty S, Kundu S (1999) On detecting bridges causing timing failures. In: Proceedings 1999 IEEE international conference on computer design: VLSI in computers and processors (Cat. No.99CB37040), pp 400\u2013406. https:\/\/doi.org\/10.1109\/ICCD.1999.808573","DOI":"10.1109\/ICCD.1999.808573"},{"key":"5714_CR28","doi-asserted-by":"publisher","unstructured":"Marella SK, Trivedi AR, Mukhopadhyay S, Sapatnekar SS (2015) Optimization of finfet-based circuits using a dual gate pitch technique. In: Proceedings of the 2015 IEEE\/ACM international conference on computer-aided design (ICCAD), pp 758\u2013763. https:\/\/doi.org\/10.1109\/ICCAD.2015.7372646","DOI":"10.1109\/ICCAD.2015.7372646"},{"key":"5714_CR29","doi-asserted-by":"publisher","unstructured":"Maxwell PC, Aitken RC, Huisman LM (1994) The effect on quality of non-uniform fault coverage and fault probability. In: Proceedings., international test conference, pp 739\u2013746. https:\/\/doi.org\/10.1109\/TEST.1994.528020","DOI":"10.1109\/TEST.1994.528020"},{"key":"5714_CR30","doi-asserted-by":"publisher","unstructured":"Natarajan S, Agostinelli M, Akbar S, Bost M, Bowonder A, Chikarmane V, Chouksey S, Dasgupta A, Fischer K, Fu Q et al (2014) A 14nm logic technology featuring 2nd-generation finfet, air-gapped interconnects, self-aligned double patterning and a 0.0588 \u03bc m2 sram cell size. In: Proceedings of the 2014 IEEE international electron devices meeting, pp 3.7.1\u20133.7.3. https:\/\/doi.org\/10.1109\/IEDM.2014.7046976","DOI":"10.1109\/IEDM.2014.7046976"},{"key":"5714_CR31","doi-asserted-by":"publisher","unstructured":"Nigh P, Gattiker A (2000) Test method evaluation experiments and data. In: Proceedings international test conference 2000 (IEEE Cat. No.00CH37159), pp 454\u2013463. https:\/\/doi.org\/10.1109\/TEST.2000.894237","DOI":"10.1109\/TEST.2000.894237"},{"issue":"12","key":"5714_CR32","doi-asserted-by":"publisher","first-page":"3055","DOI":"10.1109\/TED.2009.2032605","volume":"56","author":"K Patel","year":"2009","unstructured":"Patel K, Liu TJK, Spanos CJ (2009) Gate line edge roughness model for estimation of finfet performance variability. IEEE Transactions on Electron Devices 56(12):3055\u20133063. https:\/\/doi.org\/10.1109\/TED.2009.2032605","journal-title":"IEEE Transactions on Electron Devices"},{"key":"5714_CR33","unstructured":"Peng WP, Chi MH, Derderian G, Das K, Zhang Y, Laloe JB, Deniz D, Patil S, Yan J, Singh S et al (2016) Elimination of tungsten-voids in middle-of-line contacts for advanced planar cmos and finfet technology. In: Proceedings of the 2016 China semiconductor technology international conference (CSTIC). IEEE, pp 1\u20134"},{"key":"5714_CR34","doi-asserted-by":"publisher","unstructured":"Polian I, Engelke P, Becker B, Kundu S, Galliere JM, Renovell M (2005) Resistive bridge fault model evolution from conventional to ultra deep submicron. In: Proceedings of the 23rd IEEE VLSI test symposium (VTS\u201905), pp 343\u2013348. https:\/\/doi.org\/10.1109\/VTS.2005.72","DOI":"10.1109\/VTS.2005.72"},{"key":"5714_CR35","doi-asserted-by":"publisher","unstructured":"Rashed M, Jain N, Kim J, Tarabbia M, Rahim I, Ahmed S, Kim J, Lin I, Chan S, Yoshida H, Beasor S, Yuan L, Kye J, Chee J, Mittal A, Doman D, Johnson S, Schroeder U, Cave N, Tang T, Stephen J, Augur R, Kengeri S, Venkatesan S (2013) Innovations in special constructs for standard cell libraries in sub 28nm technologies. In: Proceedings of the 2013 IEEE international electron devices meeting, pp 9.7.1\u20139.7.4. https:\/\/doi.org\/10.1109\/IEDM.2013.6724597","DOI":"10.1109\/IEDM.2013.6724597"},{"issue":"8","key":"5714_CR36","doi-asserted-by":"publisher","first-page":"2282","DOI":"10.1109\/TED.2011.2151196","volume":"58","author":"SH Rasouli","year":"2011","unstructured":"Rasouli SH, Endo K, Chen JF, Singh N, Banerjee K (2011) Grain-orientation induced quantum confinement variation in finfets and multi-gate ultra-thin body cmos devices and implications for digital design. IEEE Transactions on Electron Devices 58(8):2282\u20132292. https:\/\/doi.org\/10.1109\/TED.2011.2151196","journal-title":"IEEE Transactions on Electron Devices"},{"key":"5714_CR37","doi-asserted-by":"publisher","unstructured":"Schuddinck P et al (2012) Standard cell level parasitics assessment in 20nm bpl and 14nm bff. In: Proceedings of the 2012 international electron devices meeting, pp 25.3.1\u201325.3.4. https:\/\/doi.org\/10.1109\/IEDM.2012.6479101","DOI":"10.1109\/IEDM.2012.6479101"},{"key":"5714_CR38","doi-asserted-by":"crossref","DOI":"10.1007\/978-94-017-7597-7","volume-title":"Variation-aware Advanced CMOS Devices and SRAM, vol 56","author":"C Shin","year":"2016","unstructured":"Shin C (2016) Variation-aware Advanced CMOS Devices and SRAM, vol 56. Springer, Berlin"},{"key":"5714_CR39","doi-asserted-by":"crossref","unstructured":"Simsir MO, Bhoj A, Jha NK (2010) Fault modeling for finfet circuits. In: Proceedings of the 2010 IEEE\/ACM international symposium on nanoscale architectures. IEEE Press, pp 41\u201346","DOI":"10.1109\/NANOARCH.2010.5510927"},{"key":"5714_CR40","doi-asserted-by":"publisher","unstructured":"Stroud CE, Emmert JM, Bailey JR, Chhor KS, Nikolic D (2000) Bridging fault extraction from physical design data for manufacturing test development. In: Proceedings international test conference 2000 (IEEE Cat. No.00CH37159), pp 760\u2013769. https:\/\/doi.org\/10.1109\/TEST.2000.894272","DOI":"10.1109\/TEST.2000.894272"},{"key":"5714_CR41","doi-asserted-by":"crossref","unstructured":"Tshagharyan G, Harutyunyan G, Shoukourian S, Zorian Y (2015) Overview study on fault modeling and test methodology development for finfet-based memories. In: Proceedings of the 2015 IEEE east-west design & test symposium (EWDTS). IEEE, pp 1\u20134","DOI":"10.1109\/EWDTS.2015.7493149"},{"key":"5714_CR42","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1016\/j.sse.2016.04.009","volume":"122","author":"X Wei","year":"2016","unstructured":"Wei X, Zhu H, Zhang Y, Zhao C (2016) Bulk finfets with body spacers for improving fin height variation. Solid State Electron 122:45\u201351. https:\/\/doi.org\/10.1016\/j.sse.2016.04.009 . http:\/\/www.sciencedirect.com\/science\/article\/pii\/S0038110116300181","journal-title":"Solid State Electron"},{"key":"5714_CR43","unstructured":"Weng CJ (2009) Defects reduction of nano-semiconductor dual damascene process development"},{"key":"5714_CR44","volume-title":"Models in hardware testing: lecture notes of the forum in honor of Christian Landrault, vol 43","author":"HJ Wunderlich","year":"2009","unstructured":"Wunderlich HJ (2009) Models in hardware testing: lecture notes of the forum in honor of Christian Landrault, vol 43. Springer Science & Business Media, Berlin"},{"issue":"5","key":"5714_CR45","doi-asserted-by":"publisher","first-page":"376","DOI":"10.1631\/jzus.C1100242","volume":"13","author":"J-J Zhu","year":"2012","unstructured":"Zhu J-J, Luo X-H, Chen L-S, Ye Y, Yan X-L (2012) Scratch-concerned yield modeling for ic manufacturing involved with a chemical mechanical polishing process. Journal of Zhejiang University SCIENCE C 13(5):376\u2013384. https:\/\/doi.org\/10.1631\/jzus.C1100242","journal-title":"Journal of Zhejiang University SCIENCE C"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-018-5714-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-018-5714-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-018-5714-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,11]],"date-time":"2019-10-11T13:15:49Z","timestamp":1570799749000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-018-5714-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,23]]},"references-count":45,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2018,4]]}},"alternative-id":["5714"],"URL":"https:\/\/doi.org\/10.1007\/s10836-018-5714-0","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2018,2,23]]},"assertion":[{"value":"28 October 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"8 February 2018","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 February 2018","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}