{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:39:30Z","timestamp":1740123570430,"version":"3.37.3"},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2018,6,6]],"date-time":"2018-06-06T00:00:00Z","timestamp":1528243200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61432017"],"award-info":[{"award-number":["61432017"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61404092"],"award-info":[{"award-number":["61404092"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61502422"],"award-info":[{"award-number":["61502422"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Zhejiang Provincial Natural Science Foundation of China","award":["LY18F020028"],"award-info":[{"award-number":["LY18F020028"]}]},{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["61772199"],"award-info":[{"award-number":["61772199"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1007\/s10836-018-5733-x","type":"journal-article","created":{"date-parts":[[2018,6,6]],"date-time":"2018-06-06T02:23:28Z","timestamp":1528251808000},"page":"447-460","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Thermal-aware SoC Test Scheduling with Voltage\/Frequency Scaling and Test Partition"],"prefix":"10.1007","volume":"34","author":[{"given":"Ying","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Ling","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianhui","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Xiao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,6,6]]},"reference":[{"issue":"4","key":"5733_CR1","doi-asserted-by":"publisher","first-page":"499","DOI":"10.1007\/s10836-013-5374-z","volume":"29","author":"N Aghaee","year":"2013","unstructured":"Aghaee N, Peng Z, Eles P (2013) Process-variation and temperature aware SoC test scheduling technique. J Electron Test 29(4):499\u2013520","journal-title":"J Electron Test"},{"issue":"5-6","key":"5733_CR2","doi-asserted-by":"publisher","first-page":"503","DOI":"10.1007\/s10836-015-5541-5","volume":"31","author":"N Aghaee","year":"2015","unstructured":"Aghaee N, Peng Z, Eles P (2015) A test-ordering based temperature-cycling acceleration technique for 3D stacked ICs. J Electron Test 31(5-6):503\u2013523","journal-title":"J Electron Test"},{"key":"5733_CR3","doi-asserted-by":"crossref","unstructured":"Bild DR, Misra S, Chantemy T, Kumar P, Dick RP, Huy XS, Shangz L, Choudhary A (2008) Temperature-aware test scheduling for multiprocessor systems-on-chip. In: Proceedings of the 2008 IEEE\/ACM International Conference on Computer-Aided Design, San Jose, USA, pp 59\u201366","DOI":"10.1109\/ICCAD.2008.4681552"},{"issue":"10","key":"5733_CR4","doi-asserted-by":"publisher","first-page":"1163","DOI":"10.1109\/43.875306","volume":"19","author":"K Chakrabarty","year":"2000","unstructured":"Chakrabarty K (2000) Test scheduling for core-based systems using mixed-integer linear programming. IEEE Trans Comput-Aid Des Integr Circuit Syst 19(10):1163\u20131174","journal-title":"IEEE Trans Comput-Aid Des Integr Circuit Syst"},{"key":"5733_CR5","doi-asserted-by":"crossref","unstructured":"Chakrabarty K (2005) Low-cost modular testing and test resource partitioning for SOCs. In: Proceedings of IEEE Computers and Digital Techniques, vol 152, pp 427\u2013441","DOI":"10.1049\/ip-cdt:20045068"},{"key":"5733_CR6","first-page":"5","volume":"2","author":"RM Chou","year":"1997","unstructured":"Chou RM, Saluja KK, Agrawal VD (1997) Scheduling tests for VLSI systems under power constraints. IEEE Trans Very Large Scale Integr Syst 2:5","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5733_CR7","unstructured":"Gurobi Optimization Inc. (2013) Gurobi optimizer erence manual. \n                    http:\/\/www.gurobi.com\n                    \n                  , Accessed 15 Apr 2014"},{"issue":"1-3","key":"5733_CR8","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1007\/s10836-007-5030-6","volume":"24","author":"Z He","year":"2008","unstructured":"He Z, Peng Z, Eles P, Rosinger P, Al-Hashimi BM (2008) Thermal-aware SoC test scheduling with test set partitioning and interleaving. J Electron Test 24(1-3):247\u2013257","journal-title":"J Electron Test"},{"issue":"10","key":"5733_CR9","doi-asserted-by":"publisher","first-page":"2616","DOI":"10.1093\/ietisy\/e89-d.10.2616","volume":"89-D","author":"Y Hu","year":"2006","unstructured":"Hu Y, Han Y, Li X, Li H, Wen X (2006) Compression\/scan Co-design for reducing test data volume, scan-in power dissipation, and test application time. IEICE Trans 89-D(10):2616\u20132625","journal-title":"IEICE Trans"},{"key":"5733_CR10","first-page":"52","volume":"12","author":"V Iyengar","year":"2003","unstructured":"Iyengar V, Chakrabarty K, Marinissen EJ (2003) Test access mechanism optimization, test scheduling, and test data volume reduction for System-on-Chip. IEEE Trans Comput 12:52","journal-title":"IEEE Trans Comput"},{"issue":"9","key":"5733_CR11","doi-asserted-by":"publisher","first-page":"1621","DOI":"10.1109\/TVLSI.2011.2160410","volume":"20","author":"L Jiang","year":"2012","unstructured":"Jiang L, Xu Q, Chakrabarty K (2012) Integrated test-architecture optimization and thermal-aware test scheduling for 3-D SoCs under pre-bond test-pin-count constraint. IEEE Trans Very Large Scale Integr Syst 20 (9):1621\u20131633","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5733_CR12","first-page":"84","volume":"4","author":"O Khan","year":"2011","unstructured":"Khan O, Kundu S (2011) Microvisor: a runtime architecture for thermal management in chip multiprocessors. Trans High-Performance Embedded Architectures Compilers 4:84\u2013110","journal-title":"Trans High-Performance Embedded Architectures Compilers"},{"key":"5733_CR13","doi-asserted-by":"crossref","unstructured":"Ling L, Jiang J (2014) Exploit Dynamic Voltage and Frequency Scaling for SoC Test Scheduling under Thermal Constraints. In: Proceedings of the 23rd IEEE Asian Test Symposium, Hangzhou, China, pp 180\u2013185","DOI":"10.1109\/ATS.2014.36"},{"key":"5733_CR14","unstructured":"Liu C, Veeraraghavan K, Iyengar V (2005) Thermal-aware test scheduling and hot spot temperature minimization for core-based system. In: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, USA, pp 552\u2013560"},{"key":"5733_CR15","doi-asserted-by":"crossref","unstructured":"Lofberg J (2004) YALMIP: a toolbox for modeling and optimization in MATLAB. In: Proceedings of CACSD Conference, Taipei, Taiwan. \n                    http:\/\/users.isy.liu.se\/johanl\/yalmip\n                    \n                  , Accessed 5 Apr 2014","DOI":"10.1109\/CACSD.2004.1393890"},{"key":"5733_CR16","doi-asserted-by":"crossref","unstructured":"Marinissen EJ, Iyengar V, Chakrabarty K (2002) A set of benchmarks for modular testing of SOCs. In: Proceedings of the 2002 IEEE International Test Conference Baltimore, USA, pp 519\u2013528","DOI":"10.1109\/TEST.2002.1041802"},{"key":"5733_CR17","unstructured":"Millican SK, Saluja KK (2012) Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits. In: Proceedings of IEEE Asian Test Symposium, Niigata, Japan, pp 37\u201342"},{"key":"5733_CR18","unstructured":"Millican SK, Saluja KK (2013) 3D-IC Benchmarks. \n                    http:\/\/3dsocbench.ece.wisc.edu\/\n                    \n                  , Accessed 20 Mar 2014"},{"key":"5733_CR19","unstructured":"Millican SK, Saluja KK (2013) Formulating optimal test scheduling problem with dynamic voltage and frequency scaling. In: Proceedings of the 22nd Asian Test Symposium, Yilan County, Taiwan, pp 165\u2013170"},{"issue":"5","key":"5733_CR20","doi-asserted-by":"publisher","first-page":"569","DOI":"10.1007\/s10836-014-5473-5","volume":"30","author":"SK Millican","year":"2014","unstructured":"Millican SK, Saluja KK (2014) Optimal test scheduling formulation under power constraints with dynamic voltage and frequency scaling. J Electr Test Theory Appl 30(5):569\u2013580","journal-title":"J Electr Test Theory Appl"},{"key":"5733_CR21","doi-asserted-by":"crossref","unstructured":"Millican SK, Saluja KK (2014) A test partitioning technique for scheduling tests for thermally constrained 3D integrated circuits. In: Proceedings of the 13th International Conference on VLSI Design and 27th International Conference on Embedded Systems, pp 20\u201325, Mumbai, India","DOI":"10.1109\/VLSID.2014.11"},{"key":"5733_CR22","unstructured":"Ravi S (2007) Power-aware test: challenges and solutions. In: Proceedings of 2007 IEEE International Test Conference, Santa Clara, USA, pp 1\u201310"},{"key":"5733_CR23","doi-asserted-by":"crossref","unstructured":"Sheshadri V, Agrawal VD, Agrawal P (2013) Power-aware SoC test optimization through dynamic voltage and frequency scaling. In: Proceedings of 21st IFIP\/IEEE International Conference on VLSI and SoC, Istanbul, Turkey, pp 102\u2013107","DOI":"10.1109\/VLSI-SoC.2013.6673258"},{"issue":"2","key":"5733_CR24","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1007\/s10836-017-5652-2","volume":"33","author":"V Sheshadri","year":"2017","unstructured":"Sheshadri V, Agrawal VD, Agrawal P (2017) Power-aware optimization of SoC test schedules using voltage and frequency scaling. J Electron Test Theory Appl 33(2):171\u2013187","journal-title":"J Electron Test Theory Appl"},{"key":"5733_CR25","unstructured":"Shih CJ, Hsu CY, Kuo CY, Li J, Rau JC, Chakrabarty K (2012) Thermal-Aware Test Schedule and TAM Co-Optimization for ThreeDimensional IC. In: Proceedings of Active and Passive Electronic Components, pp 1\u201310"},{"issue":"2","key":"5733_CR26","doi-asserted-by":"publisher","first-page":"2","DOI":"10.1145\/871656.859620","volume":"31","author":"K Skadron","year":"2003","unstructured":"Skadron K, Stan MR, Huang W, Velusamy S, Sankaranarayanan K, Tarjan D (2003) Temperature-aware microarchitecture. ACM SIGARCH Comput Architecture News 31(2):2\u201313","journal-title":"ACM SIGARCH Comput Architecture News"},{"key":"5733_CR27","first-page":"12","volume":"31","author":"S Srinivasan","year":"2012","unstructured":"Srinivasan S, Ganeshpure KP, Kundu SK (2012) A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip. IEEE Trans Comput-Aid Des Integr Circuit Syst 31:12","journal-title":"IEEE Trans Comput-Aid Des Integr Circuit Syst"},{"key":"5733_CR28","first-page":"34","volume":"4","author":"F Vartziotis","year":"2015","unstructured":"Vartziotis F, Kavousianos X, Chakrabarty K, Jain A, Parekhji R (2015) Time-division multiplexing for testing DVFS-based SoCs. IEEE Trans Comput-Aid Des Integr Circuit Syst 4:34","journal-title":"IEEE Trans Comput-Aid Des Integr Circuit Syst"},{"issue":"5","key":"5733_CR29","doi-asserted-by":"publisher","first-page":"1679","DOI":"10.1093\/ietisy\/e89-d.5.1679","volume":"89-D","author":"X Wen","year":"2006","unstructured":"Wen X, Yamashita Y, Kajihara S, Wang L, Saluja KK, Kinoshita K (2006) A new method for low-capture-power test generation for scan testing. IEICE Trans 89-D(5):1679\u20131686","journal-title":"IEICE Trans"},{"key":"5733_CR30","unstructured":"Xia Y, Chrzanowska-Jeske M, Wang B, Jeske M (2003) Using a distributed rectangle bin-packing approach for core-based SoC test scheduling with power constraints. In: Proceedings of 2003 IEEE\/ACM International Conference on Computer-Aided Design, San Jose, USA, p 100"},{"issue":"2","key":"5733_CR31","doi-asserted-by":"publisher","first-page":"317","DOI":"10.1109\/TCAD.2010.2079350","volume":"30","author":"C Yao","year":"2011","unstructured":"Yao C, Saluja KK, Ramanathan P (2011) Power and thermal constrained test scheduling under deep submicron technologies. IEEE Trans Comput-Aid Des Integr Circuit Syst 30(2):317\u2013322","journal-title":"IEEE Trans Comput-Aid Des Integr Circuit Syst"},{"key":"5733_CR32","doi-asserted-by":"crossref","unstructured":"Zhang Y, Peng Z, Jiang J, Li H, Fujita M (2015) Temperature-aware software-based self-testing for delay faults. In: Proceedings of Design Automation and Test Conference in Europe, Grenoble, France, pp 423\u2013428","DOI":"10.7873\/DATE.2015.0744"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-018-5733-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-018-5733-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-018-5733-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,5]],"date-time":"2019-06-05T19:13:04Z","timestamp":1559761984000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-018-5733-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6,6]]},"references-count":32,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2018,8]]}},"alternative-id":["5733"],"URL":"https:\/\/doi.org\/10.1007\/s10836-018-5733-x","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2018,6,6]]},"assertion":[{"value":"20 January 2018","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 April 2018","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"6 June 2018","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}