{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,15]],"date-time":"2026-03-15T01:26:39Z","timestamp":1773537999638,"version":"3.50.1"},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2018,11,12]],"date-time":"2018-11-12T00:00:00Z","timestamp":1541980800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1007\/s10836-018-5760-7","type":"journal-article","created":{"date-parts":[[2018,11,11]],"date-time":"2018-11-11T21:25:55Z","timestamp":1541971555000},"page":"735-747","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":15,"title":["Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library"],"prefix":"10.1007","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7654-263X","authenticated-orcid":false,"given":"Pablo Ilha","family":"Vaz","sequence":"first","affiliation":[]},{"given":"Thiago Hanna","family":"Both","sequence":"additional","affiliation":[]},{"given":"F\u00e1bio Fedrizzi","family":"Vidor","sequence":"additional","affiliation":[]},{"given":"Raphael Martins","family":"Brum","sequence":"additional","affiliation":[]},{"given":"Gilson In\u00e1cio","family":"Wirth","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,11,12]]},"reference":[{"issue":"6","key":"5760_CR1","doi-asserted-by":"publisher","first-page":"1690","DOI":"10.1109\/23.819140","volume":"46","author":"G Anelli","year":"1999","unstructured":"Anelli G, Campbell M, Delmastro M, Faccio F, Floria S, Giraldo A, Heijne E, Jarron P, Kloukinas K, Marchioro A, Moreira P, Snoeys W (1999) Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects. IEEE Trans Nucl Sci 46 (6):1690\u20131696","journal-title":"IEEE Trans Nucl Sci"},{"key":"5760_CR2","unstructured":"Anelli G (2000) Conception et caract\u00e9risation de circuits int\u00e9gr\u00e9s r\u00e9sistants aux radiations pour les d\u00e9tecteurs de particules du LHC en technologies CMOS submicroniques profondes, France, th\u00e8se de doctorat dirig\u00e9e par Velazco Raoul micro\u00e9lectronique Grenoble INPG 2000"},{"issue":"4","key":"5760_CR3","doi-asserted-by":"publisher","first-page":"861","DOI":"10.1109\/TNS.2005.852652","volume":"52","author":"L Chen","year":"2005","unstructured":"Chen L, Gingrich D (2005) Study of N-channel MOSFETs with an enclosed-gate layout in a 0.18 \u03bcm CMOS technology. IEEE Trans Nucl Sci 52(4):861\u2013867","journal-title":"IEEE Trans Nucl Sci"},{"key":"5760_CR4","doi-asserted-by":"crossref","unstructured":"Flores-Nigaglioni A, Contreras-Ospino BM, Ducoudray GO, Palomera R (2015) Comparative analysis and parameter extraction automation of annular MOSFETs. In: Proceedings of IEEE 58th international midwest symposium on circuits and systems (MWSCAS), pp 1\u20134","DOI":"10.1109\/MWSCAS.2015.7282108"},{"issue":"6","key":"5760_CR5","doi-asserted-by":"publisher","first-page":"981","DOI":"10.1016\/S0038-1101(00)00010-1","volume":"44","author":"A Giraldo","year":"2000","unstructured":"Giraldo A, Paccagnella A, Minzoni A (2000) Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout. Solid-State Electron 44(6):981\u2013989","journal-title":"Solid-State Electron"},{"issue":"6","key":"5760_CR6","doi-asserted-by":"publisher","first-page":"3392","DOI":"10.1109\/TNS.2006.886199","volume":"53","author":"JE Knudsen","year":"2006","unstructured":"Knudsen JE, Clark LT (2006) An area and power efficient radiation hardened by design flip-flop. IEEE Trans Nucl Sci 53(6):3392\u20133399","journal-title":"IEEE Trans Nucl Sci"},{"issue":"4","key":"5760_CR7","doi-asserted-by":"publisher","first-page":"3084","DOI":"10.1109\/TNS.2013.2268390","volume":"60","author":"MS Lee","year":"2013","unstructured":"Lee MS, Lee HC (2013) Dummy gate-assisted n-MOSFET layout for a radiation-tolerant integrated circuit. IEEE Trans Nucl Sci 60(4):3084\u20133091","journal-title":"IEEE Trans Nucl Sci"},{"issue":"12","key":"5760_CR8","doi-asserted-by":"publisher","first-page":"125009","DOI":"10.1088\/0268-1242\/24\/12\/125009","volume":"24","author":"P L\u00f3pez","year":"2009","unstructured":"L\u00f3pez P, Blanco-Filgueira B, Pardo F, Cabello D, Hauer J (2009) A 2D model for radiation-hard CMOS annular transistors. Semicond Sci Technol 24(12):125009","journal-title":"Semicond Sci Technol"},{"issue":"99","key":"5760_CR9","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TCAD.2018.2818709","volume":"PP","author":"JM Matos","year":"2018","unstructured":"Matos JM, Carrabina J, Reis A (2018) Efficiently mapping VLSI circuits with simple cells. IEEE Trans Comput-Aided Des Integr Circ Syst PP(99):1\u20131","journal-title":"IEEE Trans Comput-Aided Des Integr Circ Syst"},{"key":"5760_CR10","doi-asserted-by":"crossref","unstructured":"Mclain M, Barnaby H, Esqueda I, Oder J, Vermeire B (2009) Reliability of high performance standard two-edge and radiation hardened by design enclosed geometry transistors. In: Proceedings of IEEE international reliability physics symposium, pp 174\u2013179","DOI":"10.1109\/IRPS.2009.5173247"},{"issue":"6","key":"5760_CR11","doi-asserted-by":"publisher","first-page":"2495","DOI":"10.1109\/TNS.2005.860713","volume":"52","author":"R Nowlin","year":"2005","unstructured":"Nowlin R, McEndree S, Wilson AL, Alexander D (2005) A new total-dose-induced parasitic effect in enclosed-geometry transistors. IEEE Trans Nucl Sci 52(6):2495\u20132502","journal-title":"IEEE Trans Nucl Sci"},{"key":"5760_CR12","volume-title":"Digital integrated circuits: a design perspective","author":"J Rabaey","year":"2003","unstructured":"Rabaey J, Chandrakasan A, Nikoli\u0107 B (2003) Digital integrated circuits: a design perspective, 2nd edn. ser. Prentice Hall electronics and VLSI series, P. E., Upper Saddle River","edition":"2nd edn."},{"issue":"4","key":"5760_CR13","doi-asserted-by":"publisher","first-page":"1829","DOI":"10.1109\/TNS.2002.801534","volume":"49","author":"W Snoeys","year":"2002","unstructured":"Snoeys W, Gutierrez T, Anelli G (2002) A new NMOS layout structure for radiation tolerance. IEEE Trans Nucl Sci 49(4):1829\u20131833","journal-title":"IEEE Trans Nucl Sci"},{"key":"5760_CR14","volume-title":"Logical effort: designing fast CMOS circuits","author":"I Sutherland","year":"1999","unstructured":"Sutherland I, Sproull B, Harris D (1999) Logical effort: designing fast CMOS circuits. Morgan Kaufmann Publishers Inc., San Francisco"},{"key":"5760_CR15","volume-title":"Cadence SKILL IDE user guide","author":"CD Systems","year":"2012","unstructured":"Systems CD (2012) Cadence SKILL IDE user guide, 6th edn. Cadence Design Systems, USA","edition":"6th edn."},{"key":"5760_CR16","volume-title":"Operation and modeling of the MOS transistor, ser Oxford series in electrical and computer engineering","author":"Y Tsividis","year":"2011","unstructured":"Tsividis Y, McAndrew C (2011) Operation and modeling of the MOS transistor, ser Oxford series in electrical and computer engineering. Oxford University Press, Oxford"},{"key":"5760_CR17","unstructured":"Vaz PI, Junior AW, Wirth GI (2015) Techniques for square ELT simulation: a comparative study. In: Proceedings of IEEE 6th Latin American symposium on circuits systems (LASCAS), pp 1\u20134"},{"key":"5760_CR18","unstructured":"Vaz PI, Wirth GI (2015) Design and comparative performance simulation of RHBD inverter cells in 180nm CMOS. In: Proceedings of 30th symposium on microelectronics technology and devices (SBMicro), pp 1\u20134"},{"key":"5760_CR19","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-5646-8","volume-title":"Radiation effects on embedded systems","author":"R Velazco","year":"2007","unstructured":"Velazco R, Foillat P, Reis R, Boudenot J-C, Schrimpf RD (2007) Radiation effects on embedded systems. Springer, Dordrecht London"},{"key":"5760_CR20","volume-title":"CMOS VLSI design a circuits and systems perspective","author":"N Weste","year":"2010","unstructured":"Weste N, Harris D (2010) CMOS VLSI design a circuits and systems perspective, 4th edn. Addison-Wesley Publishing Company, Reading","edition":"4th edn."},{"issue":"8","key":"5760_CR21","first-page":"084002,08","volume":"32","author":"F Xue","year":"2011","unstructured":"Xue F, Ping L, Wei L, Bin Z, Xiaodong X, Gang W, Bin H, Yahong Z (2011) Gate-enclosed NMOS transistors. J Semicond 32(8):084002,08","journal-title":"J Semicond"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-018-5760-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-018-5760-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-018-5760-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,11,11]],"date-time":"2019-11-11T19:28:27Z","timestamp":1573500507000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-018-5760-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11,12]]},"references-count":21,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2018,12]]}},"alternative-id":["5760"],"URL":"https:\/\/doi.org\/10.1007\/s10836-018-5760-7","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,11,12]]},"assertion":[{"value":"27 June 2018","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 October 2018","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 November 2018","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}