{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:40:42Z","timestamp":1740123642727,"version":"3.37.3"},"reference-count":22,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T00:00:00Z","timestamp":1558310400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T00:00:00Z","timestamp":1558310400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.1007\/s10836-019-05797-w","type":"journal-article","created":{"date-parts":[[2019,5,21]],"date-time":"2019-05-21T10:07:19Z","timestamp":1558433239000},"page":"303-315","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS"],"prefix":"10.1007","volume":"35","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2496-6320","authenticated-orcid":false,"given":"Mahroo","family":"Zandrahimi","sequence":"first","affiliation":[]},{"given":"Philippe","family":"Debaud","sequence":"additional","affiliation":[]},{"given":"Armand","family":"Castillejo","sequence":"additional","affiliation":[]},{"given":"Zaid","family":"Al-Ars","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,5,20]]},"reference":[{"issue":"6","key":"5797_CR1","doi-asserted-by":"publisher","first-page":"725","DOI":"10.1109\/TVLSI.2008.2000257","volume":"16","author":"Z Al-Ars","year":"2008","unstructured":"Al-Ars Z et al (2008) Test set development for cache memory in modern microprocessors. IEEE Trans Very Large Scale Integration (TVLSI) Syst 16(6):725\u2013732","journal-title":"IEEE Trans Very Large Scale Integration (TVLSI) Syst"},{"key":"5797_CR2","doi-asserted-by":"crossref","unstructured":"Brockman JB, Director SW (1989) Predictive subset testing: Optimizing IC parametric performance testing for quality, cost, and yield, vol 2","DOI":"10.1109\/66.29679"},{"key":"5797_CR3","doi-asserted-by":"crossref","unstructured":"Burd TD, et al. (2000) A dynamic voltage scaled microprocessor system. In: Proceedings of the IEEE international solid-state circuits conference (ISSCC), pp 294\u2013295","DOI":"10.1109\/ISSCC.2000.839787"},{"key":"5797_CR4","doi-asserted-by":"crossref","unstructured":"Chan T, Kahng AB (2012) Tunable sensors for process-aware voltage scaling. In: Proceedings of the IEEE\/ACM international conference on computer aided design (ICCAD), pp 7\u201314","DOI":"10.1145\/2429384.2429387"},{"key":"5797_CR5","doi-asserted-by":"crossref","unstructured":"Chan T et al (2012) DDRO: a novel performance monitoring methodology based on design-dependent ring oscillators. In: Proceedings of the IEEE international symposium on quality electronic design (ISQED), pp 633\u2013640","DOI":"10.1109\/ISQED.2012.6187559"},{"key":"5797_CR6","doi-asserted-by":"crossref","unstructured":"Das P, et al. (2011) On generating vectors for accurate post-silicon delay characterization. In: Proceedings of the IEEE Asian test symposium (ATS), pp 251\u2013260","DOI":"10.1109\/ATS.2011.39"},{"key":"5797_CR7","doi-asserted-by":"crossref","unstructured":"Drake A et al (2007) A distributed critical-path timing monitor for a 65nm high-performance microprocessor. In: Proceedings of the IEEE international solid-state circuits conference (ISSCC), pp 398\u2013399","DOI":"10.1109\/ISSCC.2007.373462"},{"key":"5797_CR8","unstructured":"Goldstein LH, Thigpen EL (1980) SCOAP: Sandia controllability\/observability analysis program. In: Proceedings of the IEEE\/ACM design automation conference, pp 190\u2013 196"},{"issue":"5","key":"5797_CR9","doi-asserted-by":"publisher","first-page":"639","DOI":"10.1109\/4.997858","volume":"37","author":"J Kim","year":"2002","unstructured":"Kim J, Horowitz MA (2002) An efficient digital sliding controller for adaptive power-supply regulation. IEEE Journal of Solid-State Circuits (JSSC) 37(5):639\u2013647","journal-title":"IEEE Journal of Solid-State Circuits (JSSC)"},{"key":"5797_CR10","doi-asserted-by":"crossref","unstructured":"Kruseman B, Majhi A, Gronthoud G (2007) On performance testing with path delay patterns. In: Proceedings of the IEEE VLSI test symposium (VTS)","DOI":"10.1109\/VTS.2007.45"},{"key":"5797_CR11","unstructured":"Lee J, et al. (1999) IC performance prediction for test cost reduction. In: Proceedings of the IEEE international symposium on semiconductor manufacturing (ISSM), pp 111\u2013114"},{"key":"5797_CR12","doi-asserted-by":"crossref","unstructured":"Liu Q, Sapatnekar SS (2010) Capturing post-silicon variations using a representative critical path, vol 29","DOI":"10.1109\/TCAD.2009.2035552"},{"key":"5797_CR13","doi-asserted-by":"crossref","unstructured":"Li Zhang G, et al. (2016) EffiTest: Efficient delay test and statistical prediction for configuring post-silicon tunable buffers. In: Proceedings of the IEEE\/ACM design automation conference (DAC)","DOI":"10.1145\/2897937.2898017"},{"key":"5797_CR14","doi-asserted-by":"crossref","unstructured":"Pant P, Skeels E (2011) Hardware hooks for transition scan characterization. In: Proceedings of the IEEE international test conference (ITC), pp 1\u20138","DOI":"10.1109\/TEST.2011.6139166"},{"key":"5797_CR15","doi-asserted-by":"crossref","unstructured":"Sauer M et al (2012) On the quality of test vectors for post-silicon characterization. In: Proceedings of the IEEE European test symposium (ETS), pp 1\u20136","DOI":"10.1109\/ETS.2012.6233027"},{"key":"5797_CR16","unstructured":"Shim KN, Hu J (2012) A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience. In: Proceedings of the IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT), pp 170\u2013177"},{"key":"5797_CR17","doi-asserted-by":"crossref","unstructured":"Tehranipoor M, et al. (2011) Test and diagnosis for small-delay defects. In: Springer science+business media LLC","DOI":"10.1007\/978-1-4419-8297-1"},{"key":"5797_CR18","unstructured":"Zain Ali NB et al (2006) Dynamic voltage scaling aware delay fault testing. In: Proceedings of the IEEE European test symposium (ETS"},{"key":"5797_CR19","unstructured":"Zandrahimi M, Al-Ars Z (2014) A survey on low-power techniques for single and multicore systems. In: Proceedings of the EAI international conference on context-aware systems and applications (ICCASA), pp 69\u201374"},{"key":"5797_CR20","doi-asserted-by":"crossref","unstructured":"Zandrahimi M et al Industrial approaches for performance evaluation using on-chip monitors. In: The proceedings of the IEEE international design & test symposium (IDT 2016), 18-20 December 2016, Hammamet, Tunisia","DOI":"10.1109\/IDT.2016.7843042"},{"key":"5797_CR21","doi-asserted-by":"crossref","unstructured":"Zandrahimi M et al (2016) Challenges of using on-chip performance monitors for process and environmental variation compensation. In: Proceedings of the IEEE Design, automation and test in europe conference (DATE), pp 1018\u20131019","DOI":"10.3850\/9783981537079_0796"},{"key":"5797_CR22","doi-asserted-by":"crossref","unstructured":"Zandrahimi M et al (2017) Using transition fault test patterns for cost effective offline performance estimation. In: Proceedings of the IEEE international conference on design &technology of integrated systems in nanoscale Era (DTIS)","DOI":"10.1109\/DTIS.2017.7930174"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-019-05797-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-019-05797-w\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-019-05797-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,18]],"date-time":"2020-05-18T23:16:37Z","timestamp":1589843797000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-019-05797-w"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,20]]},"references-count":22,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2019,6]]}},"alternative-id":["5797"],"URL":"https:\/\/doi.org\/10.1007\/s10836-019-05797-w","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2019,5,20]]},"assertion":[{"value":"3 October 2018","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 April 2019","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 May 2019","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}