{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:39:08Z","timestamp":1740123548456,"version":"3.37.3"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2020,2]]},"DOI":"10.1007\/s10836-019-05852-6","type":"journal-article","created":{"date-parts":[[2020,2,18]],"date-time":"2020-02-18T11:04:03Z","timestamp":1582023843000},"page":"59-73","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration"],"prefix":"10.1007","volume":"36","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6046-7559","authenticated-orcid":false,"given":"Avishek","family":"Choudhury","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Biplab K.","family":"Sikdar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,2,18]]},"reference":[{"key":"5852_CR1","doi-asserted-by":"crossref","unstructured":"Ansari A, et al. (2009) Enabling ultra low voltage system operation by tolerating on-chip cache failures. In: Proc. ISLPED","DOI":"10.1145\/1594233.1594309"},{"key":"5852_CR2","doi-asserted-by":"crossref","unstructured":"Ansari A, et al. (2009) Enabling ultra low voltage system operation by tolerating on-chip cache failures. In: Proc. of the intl. symposium on low power electronics and design","DOI":"10.1145\/1594233.1594309"},{"key":"5852_CR3","doi-asserted-by":"crossref","unstructured":"Ansari A, et al. (2011) Archipelago: a polymorphic cache design for enabling robust near-threshold operation. In: Proc of the international conference on computer architecture (HPCA), pp 539\u2013550","DOI":"10.1109\/HPCA.2011.5749758"},{"key":"5852_CR4","doi-asserted-by":"crossref","unstructured":"BanaiyanMofrad A, et al. (2011) FFT-Cache: a flexible fault-tolerant cache architecture for ultra low voltage operation. In: Proc. CASES","DOI":"10.1145\/2038698.2038715"},{"key":"5852_CR5","doi-asserted-by":"crossref","unstructured":"BanaiyanMofrad A, et al. (2013) REMEDIATE: a scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs. In: Proc. of the international green computing conference (IGCC)","DOI":"10.1109\/IGCC.2013.6604500"},{"issue":"2","key":"5852_CR6","doi-asserted-by":"publisher","first-page":"Article 32","DOI":"10.1145\/2629566","volume":"14","author":"A Banaiyanmofrad","year":"2015","unstructured":"Banaiyanmofrad A, Homayoun H, Dutt N (2015) Using a flexible fault- tolerant cache to improve reliability for ultra low voltage operation. ACM Trans Embedded Comput Syst 14(2):Article 32. Publication date: February 2015","journal-title":"ACM Trans Embedded Comput Syst"},{"key":"5852_CR7","unstructured":"Calhoun B, Chandrakasan A (2006) A 256 kb subthreshold SRAM in 65nm CMOS. In: Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp 480\u201348"},{"key":"5852_CR8","doi-asserted-by":"crossref","unstructured":"Chen C, Hsiao M (1984) Error-correcting codes for semiconductor memory applications: a state of the art review. IBM J R & D","DOI":"10.1147\/rd.282.0124"},{"key":"5852_CR9","doi-asserted-by":"crossref","unstructured":"Choudhury A, Sikdar BK Modeling and analysis of redundancy based fault tolerance for permanent faults in chip multiprocessor cache. In: Proceedings of the 31st international conference on VLSI design, VLSID 2018, ISSN-2380-6923, pp 115\u2013120","DOI":"10.1109\/VLSID.2018.47"},{"key":"5852_CR10","doi-asserted-by":"crossref","unstructured":"Choudhury A, Sikdar BK (2017) CIFR: a complete in-place fault remapping strategy for CMP cache for dynamic reuse distance. In: Proc. of the 7th International conference on embedded computing and system design, ISED","DOI":"10.1109\/ISED.2017.8303922"},{"key":"5852_CR11","doi-asserted-by":"crossref","unstructured":"Duong N, et al. (2012) Improving cache management policies using dynamic reuse distances. In: Proceedings of the 45th Annual IEEE\/ACM international symposium on microarchitecture (MICRO)","DOI":"10.1109\/MICRO.2012.43"},{"key":"5852_CR12","doi-asserted-by":"crossref","unstructured":"Kim J, Hardavellas N, Mai K, Falsafi B, Hoe JC (2007) Multi-bit error tolerant caches using two-dimensional error coding. In: Proc. 39th annual IEEE\/ACM international symposium on microarchitecture (MICRO 39), pp 15\u201325","DOI":"10.1109\/MICRO.2007.19"},{"key":"5852_CR13","doi-asserted-by":"crossref","unstructured":"Koh C-K, et al. (2009) The salvage cache: a fault-tolerant cache architecture for next-generation memory technologies. In: Proc. of the international conference on computer design (ICCD)","DOI":"10.1109\/ICCD.2009.5413145"},{"key":"5852_CR14","doi-asserted-by":"crossref","unstructured":"Kulkarni JP, Kim K, Roy K (2007) A 160 mv, fully differential, robust Schmitt trigger based sub-threshold sram. In: Proc. of the 2007 international symposium on low power electronics and design. ACM, New York, pp 171\u2013176","DOI":"10.1145\/1283780.1283818"},{"key":"5852_CR15","doi-asserted-by":"crossref","unstructured":"Ladas N, Sazeides Y, Desmet V (2010) Performance-effective operation below Vcc-min. In: Proc of the intl symposium on performance analysis of systems & software","DOI":"10.1109\/ISPASS.2010.5452017"},{"key":"5852_CR16","doi-asserted-by":"crossref","unstructured":"Moradi F, Wisland D, Aunet S, Mahmoodi H, Cao T (2008) 65nm sub-threshold 11t-sram for ultra low voltage applications. In: Intl. symposium on system-on-a-chip, p 113118","DOI":"10.1109\/SOCC.2008.4641491"},{"key":"5852_CR17","doi-asserted-by":"crossref","unstructured":"Morita Y, Fujiwara H, Noguchi H, Iguchi Y, Nii K, Kawaguchi H, Yoshimoto M (2007) An area-conscious low-voltage-oriented 8t-sram design under dvs environment. IEEE Symposium on VLSI circuits, pp. 256\u2013257","DOI":"10.1109\/VLSIC.2007.4342741"},{"key":"5852_CR18","doi-asserted-by":"crossref","unstructured":"Ozdemir S, Sinha D, Memik G, Adams J, Zhou H (2006) Yield-aware cache architectures. In: Proc. of the international symposium on microarchitecture","DOI":"10.1109\/MICRO.2006.52"},{"key":"5852_CR19","doi-asserted-by":"crossref","unstructured":"Pour F, Hill MD (1993) Performance implications of tolerating cache faults, Trans Comput","DOI":"10.1109\/12.210168"},{"issue":"4","key":"5852_CR20","first-page":"Article 29","volume":"10","author":"D Sa\u2019nchez","year":"2013","unstructured":"Sa\u2019nchez D, Sazeides Y, Cebria\u2019n J, Garc\u2019ia JM, Arago\u2019 JLN (2013) Modeling the impact of permanent faults in caches. ACM Trans Arch Code Optim 10(4):Article 29. Publication date: December 2013","journal-title":"ACM Trans Arch Code Optim"},{"key":"5852_CR21","doi-asserted-by":"crossref","unstructured":"Sasan A, Homayoun H, Eltawil A, Kurdahi F (2009) A fault tolerant cache architecture for sub 500mv operation: resizable data composer cache (RDC-Cache). In: Proc. of international conference on compilers, architectures and synthesis for embedded systems (CASES)","DOI":"10.1145\/1629395.1629431"},{"issue":"1","key":"5852_CR22","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/MCD.2005.1388765","volume":"21","author":"T Skotnicki","year":"2005","unstructured":"Skotnicki T, Hutchby J, King T-J, Wong H-S, Boeuf F (2005) The end of cmos scaling: toward the introduction of new materials and structural changes to improve mosfet performance. Circ Dev Mag IEEE 21(1):16","journal-title":"Circ Dev Mag IEEE"},{"issue":"4","key":"5852_CR23","doi-asserted-by":"publisher","first-page":"484","DOI":"10.1109\/12.21141","volume":"38","author":"G Sohi","year":"1989","unstructured":"Sohi G (1989) Cache memory organization to enhance the yield of high-performance VLSI processors. IEEE Trans. Computers 38(4):484\u2013492","journal-title":"IEEE Trans. Computers"},{"key":"5852_CR24","doi-asserted-by":"crossref","unstructured":"Ubal R, Jang B, Mistry P, Schaa D, Kaeli D (2012) Multi2Sim: a simulation framework for CPU-GPU computing. In: Proc. of 21st international conference on parallel architectures and compilation techniques. Minneapolis","DOI":"10.1145\/2370816.2370865"},{"key":"5852_CR25","unstructured":"Vergos HT, Nikolos D (1995) Performance recovery in direct- mapped faulty caches via the use of a very small fully associative spare cache. In: Proc. of the intl. computer performance and dependability symposium"},{"key":"5852_CR26","doi-asserted-by":"crossref","unstructured":"Wilkerson C et al (2008) Trading off cache capacity for reliability to enable low voltage operation. In: Proc. of international symposium on computer architecture (ISCA)","DOI":"10.1109\/ISCA.2008.22"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-019-05852-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-019-05852-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-019-05852-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,2,19]],"date-time":"2021-02-19T05:20:44Z","timestamp":1613712044000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-019-05852-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2]]},"references-count":26,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2020,2]]}},"alternative-id":["5852"],"URL":"https:\/\/doi.org\/10.1007\/s10836-019-05852-6","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2020,2]]},"assertion":[{"value":"11 August 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 December 2019","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 February 2020","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}