{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:39:31Z","timestamp":1740123571808,"version":"3.37.3"},"reference-count":43,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2020,2]]},"DOI":"10.1007\/s10836-020-05856-7","type":"journal-article","created":{"date-parts":[[2020,3,20]],"date-time":"2020-03-20T02:03:08Z","timestamp":1584669788000},"page":"87-103","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors"],"prefix":"10.1007","volume":"36","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6344-3875","authenticated-orcid":false,"given":"Adeboye Stephen","family":"Oyeniran","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raimund","family":"Ubar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maksim","family":"Jenihhin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaan","family":"Raik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,3,20]]},"reference":[{"issue":"1","key":"5856_CR1","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1109\/PGEC.1966.264376","volume":"EC-15","author":"DB Armstrong","year":"1966","unstructured":"Armstrong DB (1966) On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets. IEEE Trans Electr Comput EC-15(1):66\u201373","journal-title":"IEEE Trans Electr Comput"},{"key":"5856_CR2","doi-asserted-by":"crossref","unstructured":"Bernardi P et al (2014) On the in-field functional testing of decode units in pipelined RISC processors. Proceedings of 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, pp 299\u2013304","DOI":"10.1109\/DFT.2014.6962090"},{"key":"5856_CR3","doi-asserted-by":"crossref","unstructured":"Bernardi P, Ciganda L, Grosso M, Sanchez E, Sonza Reorda M (2012) A SBST strategy to test microprocessors\u2019 Branch Target Buffer. Proceedings of 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), pp 306\u2013311","DOI":"10.1109\/DDECS.2012.6219079"},{"key":"5856_CR4","doi-asserted-by":"crossref","unstructured":"Bernardi P, Cantoro R, Ciganda L, Du B, Sanchez E, Reorda MS, Grosso M, Ballan O (2013) On the functional test of the register forwarding and pipeline interlocking unit in pipelined processors. Proceedings of 14th International Workshop on Microprocessor Test and Verification, pp 52\u201357","DOI":"10.1109\/MTV.2013.10"},{"issue":"1","key":"5856_CR5","doi-asserted-by":"publisher","first-page":"108","DOI":"10.1145\/606603.606609","volume":"8","author":"RD Blanton","year":"2003","unstructured":"Blanton RD, Hayes JP (2003) On the properties of the input pattern fault model. ACM Trans Des Autom Electron Syst 8(1):108\u2013124","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"5856_CR6","first-page":"690","volume-title":"Essentials of electronic testing for digital, memory and Mixed-Signal VLSI circuits","author":"M Bushnell","year":"2013","unstructured":"Bushnell M, Agrawal V (2013) Essentials of electronic testing for digital, memory and Mixed-Signal VLSI circuits. Springer, Berlin, p 690"},{"key":"5856_CR7","doi-asserted-by":"crossref","unstructured":"Corno F, Cumani G, Sonza Reorda M, Squillero G (2000) An RT-level fault model with high gate level correlation. Proceedings of IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786), Berkeley, pp 3\u20138","DOI":"10.1109\/HLDVT.2000.889551"},{"issue":"2","key":"5856_CR8","doi-asserted-by":"publisher","first-page":"102","DOI":"10.1109\/MDT.2004.1277902","volume":"21","author":"F Corno","year":"2004","unstructured":"Corno F, Sanchez E, Reorda MS, Squillero G (2004) Automatic test program generation: a case study. IEEE Des Test Comput 21(2):102\u2013109","journal-title":"IEEE Des Test Comput"},{"key":"5856_CR9","unstructured":"Cho CH, Armstrong JR (1994) B-algorithm: a behavioral test generation algorithm. Proceedings of International Test Conference, Washington, pp 968\u2013979"},{"key":"5856_CR10","unstructured":"Cho KY, Mitra S, McCluskey EJ (2005) Gate exhaustive testing. Proceedings of IEEE International Conference on Test, Austin, pp 7\u2013777"},{"key":"5856_CR11","unstructured":"Dwarakanath KN, Blanton RD (2000) Universal fault simulation using fault tuples. Proceedings of 37th Design Automation Conference, Los Angeles, pp 786\u2013789"},{"key":"5856_CR12","doi-asserted-by":"crossref","unstructured":"Georgiou P, Kavousianos X, Cantoro R, Reorda MS (2018) Fault-Independent Test-Generation For Software-Based Self-Testing. Proceedings of 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Platja d\u2019Aro, pp 79\u201384","DOI":"10.1109\/IOLTS.2018.8474081"},{"issue":"11","key":"5856_CR13","doi-asserted-by":"publisher","first-page":"1441","DOI":"10.1109\/TVLSI.2008.2000866","volume":"16","author":"D Gizopoulos","year":"2008","unstructured":"Gizopoulos D et al (2008) Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(11):1441\u20131453","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"issue":"9","key":"5856_CR14","doi-asserted-by":"publisher","first-page":"1396","DOI":"10.1109\/TCAD.2014.2323216","volume":"33","author":"F Hapke","year":"2014","unstructured":"Hapke F, Redemund W, Glowatz A, Rajski J, Reese M, Hustava M, Keim M, Schloeffel J, Fast A (2014) Cell-Aware Test. IEEE Trans Comput-Aided Des Integr Circ Syst 33(9):1396\u20131409","journal-title":"IEEE Trans Comput-Aided Des Integr Circ Syst"},{"key":"5856_CR15","doi-asserted-by":"crossref","unstructured":"Holst S, Wunderlich H (2007) Adaptive debug and diagnosis without fault dictionaries. Proceedings of 12th IEEE European Test Symposium (ETS\u201907), Freiburg, pp 7\u201312","DOI":"10.1109\/ETS.2007.9"},{"key":"5856_CR16","doi-asserted-by":"crossref","unstructured":"Jas A, Natarajan S, Patil S (2007) The Region-Exhaustive fault model. Proceedings of 16th Asian Test Symposium (ATS 2007), Beijing, pp 13\u201318","DOI":"10.1109\/ATS.2007.78"},{"key":"5856_CR17","unstructured":"Keller KB (1994) Hierarchical Pattern Faults for Describing Logic Circuit Failure Mechanisms. US Patent 5546408"},{"issue":"4","key":"5856_CR18","doi-asserted-by":"publisher","first-page":"461","DOI":"10.1109\/TC.2005.68","volume":"54","author":"N Kranitis","year":"2005","unstructured":"Kranitis N, Paschalis A, Gizopoulos D, Xenoulis G (2005) Software-based self-testing of embedded processors. IEEE Trans Comput 54(4):461\u2013475","journal-title":"IEEE Trans Comput"},{"key":"5856_CR19","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5597-1","volume-title":"Delay Fault Testing for VLSI Circuits","author":"A Kristic","year":"1998","unstructured":"Kristic A, Cheng KT (1998) Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers, Dordrecht"},{"issue":"5","key":"5856_CR20","first-page":"2017","volume":"1","author":"V Kumar","year":"2012","unstructured":"Kumar V, et al. (2012) Employing functional analysis to study fault models in VHDL. Int J Sci Eng Technol 1(5):2017\u2013208","journal-title":"Int J Sci Eng Technol"},{"key":"5856_CR21","unstructured":"Lee HK, Ha DS (1990) SOPRANO: An efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits. Proceedings of 27th ACM\/IEEE Design Automation Conference, Orlando, pp 660\u2013666"},{"key":"5856_CR22","unstructured":"Li Z, Lu X, Qiu W, Shi W, Walker DMH (2003) A circuit level fault model for resistive opens and bridges. Proceedings of 21st VLSI Test Symposium, Napa, pp 379\u2013384"},{"key":"5856_CR23","doi-asserted-by":"crossref","unstructured":"Mahlstedt U, Alt J, Hollenbeck I (1995) Deterministic test generation for non-classical faults on the gate level. Proceedings of Fourth Asian Test Symposium, Bangalore, pp 244\u2013251","DOI":"10.1109\/ATS.1995.485343"},{"key":"5856_CR24","unstructured":"OpenCores, \u201cMiniMIPS ISA\u201d"},{"key":"5856_CR25","doi-asserted-by":"crossref","unstructured":"Oyeniran AS, Ubar R, Azad SP, Raik J (2017) High-level test generation for processing elements in many-core systems. Proceedings of 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Madrid, pp 1\u20138","DOI":"10.1109\/ReCoSoC.2017.8016156"},{"key":"5856_CR26","doi-asserted-by":"crossref","unstructured":"Oyeniran AS, Azad SP, Ubar R (2018) Parallel Pseudo-Exhaustive testing of array multipliers with Data-Controlled segmentation. Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, pp 1\u20135","DOI":"10.1109\/ISCAS.2018.8350936"},{"key":"5856_CR27","doi-asserted-by":"crossref","unstructured":"Oyeniran AS, Ubar R, Jenihhin M, G\u00fcrsoy CC, Raik J (2019) Mixed-level identification of fault redundancy in microprocessors. Proceedings of 2019 IEEE Latin American Test Symposium (LATS), Santiago, pp 1\u20136","DOI":"10.1109\/LATW.2019.8704591"},{"key":"5856_CR28","doi-asserted-by":"crossref","unstructured":"Oyeniran AS, Ubar R, Jenihhin M, G\u00fcrsoy CC, Raik J (2019) High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. 2019 IEEE European Test Symposium (ETS), Baden-Baden, pp 1\u20136","DOI":"10.1109\/ETS.2019.8791526"},{"issue":"10","key":"5856_CR29","doi-asserted-by":"publisher","first-page":"1083","DOI":"10.1109\/12.888044","volume":"49","author":"M Psarakis","year":"2000","unstructured":"Psarakis M, Gizopoulos D, Paschalis A, Zorian Y (2000) Sequential fault modeling and test pattern generation for CMOS iterative logic arrays. IEEE Trans Comput 49(10):1083\u20131099","journal-title":"IEEE Trans Comput"},{"key":"5856_CR30","doi-asserted-by":"crossref","unstructured":"Raik J, Ubar R, Sudbrock J, Kuzmicz W, Pleskacz W (2005) DOT: New deterministic defect-oriented ATPG tool. Proceedings of European Test Symposium (ETS\u201905), Tallinn, pp 96\u2013101","DOI":"10.1109\/ETS.2005.15"},{"key":"5856_CR31","doi-asserted-by":"crossref","unstructured":"Riefert A, Cantoro R, Sauer M, Reorda MS, Becker B (2015) On the automatic generation of SBST test programs for in-field test. Proceedings of 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, pp 1186\u20131191","DOI":"10.7873\/DATE.2015.0271"},{"issue":"4","key":"5856_CR32","doi-asserted-by":"publisher","first-page":"278","DOI":"10.1147\/rd.104.0278","volume":"10","author":"JP Roth","year":"1966","unstructured":"Roth JP (1966) Diagnosis of Automata Failures: A Calculus and a method. IBM J Res Dev 10(4):278\u2013291","journal-title":"IBM J Res Dev"},{"issue":"9","key":"5856_CR33","doi-asserted-by":"publisher","first-page":"1675","DOI":"10.1109\/TVLSI.2014.2356612","volume":"23","author":"E Sanchez","year":"2015","unstructured":"Sanchez E, Reorda MS (2015) On the Functional Test of Branch Prediction Units. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(9):1675\u20131688","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"5856_CR34","unstructured":"Sch\u00f6lzel M (2015) Self-Testing and Self-Repairing Embedded Processors: Techniques for statically scheduled superscalar architectures. Habilitation thesis. Brandenburg University of Technology Cottbus-Seftenberg"},{"issue":"10","key":"5856_CR35","doi-asserted-by":"publisher","first-page":"1288","DOI":"10.1109\/12.5992","volume":"37","author":"L Shen","year":"1988","unstructured":"Shen L, Su S (1988) A Functional Testing Method for Microprocessors. IEEE Trans Comput 37(10):1288\u20131293","journal-title":"IEEE Trans Comput"},{"issue":"6","key":"5856_CR36","doi-asserted-by":"publisher","first-page":"429","DOI":"10.1109\/TC.1980.1675602","volume":"C-29","author":"SM Thatte","year":"1980","unstructured":"Thatte SM, Abraham JA (1980) Test Generation for Microprocessors. IEEE Trans Comput C-29(6):429\u2013441","journal-title":"IEEE Trans Comput"},{"key":"5856_CR37","doi-asserted-by":"crossref","unstructured":"Thaker PA, Agrawal VD, Zaghloul ME (2000) Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. Proceedings of International Test Conference 2000 (IEEE Cat. No.00CH37159), Atlantic City, pp 940\u2013949","DOI":"10.1109\/TEST.2000.894305"},{"issue":"11","key":"5856_CR38","first-page":"part 2","volume":"40","author":"R Ubar","year":"1980","unstructured":"Ubar R (1980) Fault Diagnosis in Combinational Circuits by Solving Boolean Differential Equations. Autom Remote Control 40(11):part 2. Plenum publishing corporation, USA, pp 1693\u20131703","journal-title":"Autom Remote Control"},{"key":"5856_CR39","doi-asserted-by":"crossref","unstructured":"Ubar R, Kostin S, Raik J (2012) How to prove that a circuit is Fault-Free?. Proceedings of 2012 15th Euromicro Conference on Digital System Design, Izmir, pp 427\u2013430","DOI":"10.1109\/DSD.2012.75"},{"key":"5856_CR40","unstructured":"van de Goor AJ (1991) Testing Semiconductor memories. Theory and practice. Wiley, New York, p 512"},{"key":"5856_CR41","unstructured":"Wang L.-T., Wu Ch.-W., Wen X (2006) VLSI Test Principles and Architectures. Design for testability. Elsevier, pp 777"},{"key":"5856_CR42","doi-asserted-by":"crossref","unstructured":"Wen CH, Wang LC, Cheng K-T (2005) Simulation-based functional test generation for embedded processors. Proceedings of Tenth IEEE International High-Level Design Validation and Test Workshop, Napa Valley, pp 3\u201310","DOI":"10.1109\/HLDVT.2005.1568806"},{"issue":"7","key":"5856_CR43","doi-asserted-by":"publisher","first-page":"1220","DOI":"10.1109\/TVLSI.2012.2208130","volume":"21","author":"Y Zhang","year":"2013","unstructured":"Zhang Y, Li H, Li X (2013) Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(7):1220\u20131233","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-020-05856-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-020-05856-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-020-05856-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,3,20]],"date-time":"2021-03-20T01:07:46Z","timestamp":1616202466000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-020-05856-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2]]},"references-count":43,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2020,2]]}},"alternative-id":["5856"],"URL":"https:\/\/doi.org\/10.1007\/s10836-020-05856-7","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2020,2]]},"assertion":[{"value":"9 August 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 January 2020","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 March 2020","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}