{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:35:12Z","timestamp":1774366512772,"version":"3.50.1"},"reference-count":41,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2020,2]]},"DOI":"10.1007\/s10836-020-05859-4","type":"journal-article","created":{"date-parts":[[2020,2,3]],"date-time":"2020-02-03T13:03:26Z","timestamp":1580735006000},"page":"123-133","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":12,"title":["Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures"],"prefix":"10.1007","volume":"36","author":[{"given":"Soham","family":"Roy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brandon","family":"Stiene","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3682-4610","authenticated-orcid":false,"given":"Spencer K.","family":"Millican","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vishwani D.","family":"Agrawal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,2,3]]},"reference":[{"issue":"11","key":"5859_CR1","doi-asserted-by":"publisher","first-page":"864","DOI":"10.1109\/TC.1979.1675267","volume":"C-28","author":"M Abramovici","year":"1979","unstructured":"Abramovici M, Breuer MA (1979) On redundancy and fault detection in sequential circuits. IEEE Transactions on Computers C-28(11):864\u2013865","journal-title":"IEEE Transactions on Computers"},{"issue":"10","key":"5859_CR2","doi-asserted-by":"publisher","first-page":"2949","DOI":"10.1109\/TVLSI.2017.2717844","volume":"25","author":"C Acero","year":"2017","unstructured":"Acero C, Feltham D, Liu Y, Moghaddam E, Mukherjee N, Patyra M, Rajski J, Reddy SM, Tyszer J, Zawada J (2017) Embedded deterministic test points. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25(10):2949\u20132961","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"5859_CR3","unstructured":"Bakshi D (2012) Techniques for seed computation and testability enhancement for logic built-in self test. Master\u2019s thesis, Virginia Tech"},{"key":"5859_CR4","volume-title":"Built-in test for VLSI: pseudorandom techniques","author":"PH Bardell","year":"1987","unstructured":"Bardell PH, McAnney WH, Savir J (1987) Built-in test for VLSI: pseudorandom techniques. Wiley-Interscience, New York"},{"key":"5859_CR5","unstructured":"Brglez F (1984) On testability analysis of combinational networks. In: Proceedings of the international symposium on circuits and systems (ISCAS), vol 1, pp 221\u2013225"},{"key":"5859_CR6","unstructured":"Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark circuits and a targeted translator in fortran. In: Proceedings of the IEEE Int. symposium on circuits and systems (ISCAS), pp 677\u2013692"},{"key":"5859_CR7","unstructured":"Briers AJ, Totton KAE (1986) Random pattern testability by fast fault simulation. In: Proceedings of IEEE international test conference (ITC)"},{"key":"5859_CR8","unstructured":"Cheng K-T, Lin C-J (1995) Timing-driven test point insertion for full-scan and partial-scan BIST. In: Proceedings of the IEEE international test conference (ITC), pp 506\u2013514"},{"issue":"3","key":"5859_CR9","doi-asserted-by":"publisher","first-page":"44","DOI":"10.1109\/54.867894","volume":"17","author":"F Corno","year":"2000","unstructured":"Corno F, Reorda MS, Squillero G (2000) RT-level ITC\u201999 benchmarks and first ATPG results. IEEE Design & Test of Computers 17(3):44\u201353","journal-title":"IEEE Design & Test of Computers"},{"issue":"9","key":"5859_CR10","doi-asserted-by":"publisher","first-page":"830","DOI":"10.1109\/TC.1986.1676843","volume":"35","author":"R David","year":"1986","unstructured":"David R (1986) Signature analysis for multiple-output circuits. IEEE Trans Comput 35(9):830\u2013837","journal-title":"IEEE Trans Comput"},{"key":"5859_CR11","unstructured":"Dervisoglu BI, Stong GE (1991) Design for testability using scanpath techniques for path-delay test and measurement. In: Proc IEEE International Test Conference, pp 365\u2013374"},{"key":"5859_CR12","doi-asserted-by":"crossref","unstructured":"Fang Y, Albicki A (1995) Efficient testability enhancement for combinational circuit. In: Proceedings of international conference on computer design (ICCD), pp 168\u2013172","DOI":"10.1109\/ICCD.1995.528806"},{"key":"5859_CR13","doi-asserted-by":"crossref","unstructured":"Geuzebroek MJ, van der Linden JT, van de Goor AJ (2002) Test point insertion that facilitates ATPG in reducing test time and data volume. In: Proceedings of the IEEE international test conference, Washington, DC, USA, pp 138\u2013147","DOI":"10.1109\/TEST.2002.1041754"},{"key":"5859_CR14","doi-asserted-by":"crossref","unstructured":"Ghani T, Mistry K, Packan P, Thompson S, Stettler M, Tyagi S, Bohr M (2000) Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors. In: Proc Symposium on VLSI Technology, pp 174\u2013175","DOI":"10.1109\/VLSIT.2000.852814"},{"issue":"7","key":"5859_CR15","doi-asserted-by":"publisher","first-page":"727","DOI":"10.1109\/T-C.1974.224021","volume":"C-23","author":"JP Hayes","year":"1974","unstructured":"Hayes JP, Friedman AD (1974) Test point placement to simplify fault detection. IEEE Trans Comput C-23(7):727\u2013735","journal-title":"IEEE Trans Comput"},{"key":"5859_CR16","doi-asserted-by":"crossref","unstructured":"He M, Gustavo K, Contreas, Tran D, Winemberg L, Tehranipoor M (2017) Test-point insertion efficiency analysis for LBIST in high-assurance applications. IEEE Transactions on Very Large Scale Integration 25(9)","DOI":"10.1109\/TVLSI.2017.2704104"},{"key":"5859_CR17","unstructured":"Higgins FP, Srinivasan R (2000) BSM2: Next generation boundary-scan master. In: Proc 18th IEEE VLSI Test Symposium (VTS), pp 67\u201372"},{"key":"5859_CR18","unstructured":"Iyengar VS, Brand D (1989) Synthesis of pseudo-random pattern testable designs. In: Proceedings of the international test conference, pp 501\u2013508"},{"key":"5859_CR19","doi-asserted-by":"crossref","unstructured":"Karpovsky MG, Gupta SK, Pradhan DK (1991) Aliasing and diagnosis probability in misr and stumps using a general error model. In: Proceedings of the international test conference, Nashville, TN, pp 828\u2013839","DOI":"10.1109\/TEST.1991.519748"},{"key":"5859_CR20","doi-asserted-by":"crossref","unstructured":"Mahmod J, Millican SK, Guin U, Agrawal VD (2019) Special session: delay fault testing - present and future. Proceedings of the 37th VLSI Test Symposium (VTS), Monterey, CA","DOI":"10.1109\/VTS.2019.8758662"},{"key":"5859_CR21","unstructured":"Majhi AK, Agrawal VD (1998) Delay fault models and coverage. In: Proc 11th international conference on VLSI Design, Chennai, India, pp 364\u2013369"},{"key":"5859_CR22","unstructured":"Makar SR, McCluskey EJ (1995) Functional tests for scan chain latches. In: Proceedings of international test conference (ITC), pp 606\u2013615"},{"issue":"13","key":"5859_CR23","first-page":"28","volume":"54","author":"R Mattiuzzo","year":"2009","unstructured":"Mattiuzzo R, Appello D, Allsup C (2009) Small-delay-defect testing. EDN (Electrical Design News) 54 (13):28","journal-title":"EDN (Electrical Design News)"},{"key":"5859_CR24","unstructured":"Millican SK (2019) OpenEDA. Online. Available: https:\/\/github.com\/vlsi-test-lab\/OpenEDA"},{"issue":"1","key":"5859_CR25","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1109\/54.980051","volume":"19","author":"PK Nag","year":"2002","unstructured":"Nag PK, Gattiker A, Wei S, Blanton RD, Maly W (2002) Modeling the economics of testing: a DFT perspective. IEEE Design & Test of Computers 19(1):29\u201341","journal-title":"IEEE Design & Test of Computers"},{"key":"5859_CR26","doi-asserted-by":"crossref","unstructured":"Nigh P, Needham W, Butler K, Maxwell P, Aitken R (1997) An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. In: Proc 15th IEEE VLSI Test Symposium, pp 459\u2013464","DOI":"10.1109\/VTEST.1997.600334"},{"issue":"5","key":"5859_CR27","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/MDT.2003.1232253","volume":"20","author":"S Pateras","year":"2003","unstructured":"Pateras S (2003) Achieving at-speed structural test. IEEE Design and Test of Computers 20(5):26\u201333","journal-title":"IEEE Design and Test of Computers"},{"key":"5859_CR28","volume-title":"Arithmetic built-in self-test for embedded systems","author":"J Rajski","year":"1998","unstructured":"Rajski J, Tyszer J (1998) Arithmetic built-in self-test for embedded systems. Prentice-Hall Inc., Upper Saddle River"},{"key":"5859_CR29","doi-asserted-by":"crossref","unstructured":"Ren H, Kusko M, Kravets V, Yaari R (2009) Low cost test point insertion without using extra registers for high performance design. In: Proceedings of the International Test Conference (ITC), Austin, TX","DOI":"10.1109\/TEST.2009.5355747"},{"key":"5859_CR30","doi-asserted-by":"crossref","unstructured":"Roy S, Stiene B, Millican SK, Agrawal VD (2019) Improved random pattern delay fault coverage using inversion test points. In: IEEE 28th North Atlantic Test Workshop (NATW), pp 206\u2013211","DOI":"10.1109\/NATW.2019.8758727"},{"issue":"8","key":"5859_CR31","doi-asserted-by":"publisher","first-page":"1051","DOI":"10.1109\/43.298041","volume":"13","author":"EM Rudnick","year":"1994","unstructured":"Rudnick EM, Chickermane V, Patel JH (1994) An observability enhancement approach for improved testability and at-speed test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13 (8):1051\u20131056","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"5859_CR32","doi-asserted-by":"crossref","unstructured":"Savaria Y, Youssef M, Kaminska B, Koudil M (1991) Automatic test point insertion for pseudo-random testing. In: Proceedings of the IEEE international sympoisum on circuits and systems (ISCAS), vol 4, pp 1960\u20131963","DOI":"10.1109\/ISCAS.1991.176793"},{"key":"5859_CR33","doi-asserted-by":"crossref","unstructured":"Sayil S (2018) Conventional test methods. In: Contactless VLSI measurement and testing techniques. Springer, pp 1\u20137","DOI":"10.1007\/978-3-319-69673-7_1"},{"key":"5859_CR34","doi-asserted-by":"publisher","first-page":"259","DOI":"10.1016\/j.microrel.2018.07.032","volume":"87","author":"W Sootkaneung","year":"2018","unstructured":"Sootkaneung W, Howimanporn S, Chookaew S (2018) Temperature effects on BTI and soft errors in modern logic circuits. Microelectronics Reliability 87:259\u2013270","journal-title":"Microelectronics Reliability"},{"issue":"4","key":"5859_CR35","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1109\/EDL.1983.25667","volume":"4","author":"E Takeda","year":"1983","unstructured":"Takeda E, Suzuki N (1983) An empirical model for device degradation due to hot-carrier injection. IEEE Electron Device Letters 4(4):111\u2013113","journal-title":"IEEE Electron Device Letters"},{"key":"5859_CR36","doi-asserted-by":"crossref","unstructured":"Tamarapalli N, Rajski J (1996) Constructive multi-phase test point insertion for scan-based bist. In: Proceedings of the International Test Conference (ITC), pp 649\u2013658","DOI":"10.1109\/TEST.1996.557122"},{"key":"5859_CR37","unstructured":"Touba NA, McCluskey EJ (1994) Automated logic synthesis of random pattern testable circuits. In: Proceedings of the IEEE international test conference (ITC), pp 174\u2013183"},{"key":"5859_CR38","doi-asserted-by":"crossref","unstructured":"Tsai HC, Cheng K-T, Lin CJ, Bhawmik S (1997) A hybrid algorithm for test point selection for scan-based BIST. In: Proceedings of the 34th design automation conference (DAC), pp 478\u2013483","DOI":"10.1109\/DAC.1997.597195"},{"issue":"3","key":"5859_CR39","doi-asserted-by":"publisher","first-page":"942","DOI":"10.1109\/TVLSI.2016.2606248","volume":"25","author":"D Xiang","year":"2017","unstructured":"Xiang D, Wen X, Wang L (2017) Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3):942\u2013953","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"10","key":"5859_CR40","doi-asserted-by":"publisher","first-page":"1473","DOI":"10.1109\/TC.2011.189","volume":"61","author":"J Yang","year":"2012","unstructured":"Yang J, Touba NA, Nadeau-Dostie B (2012) Test point insertion with control points driven by existing functional flip-flops. IEEE Trans Comput 61(10):1473\u20131483","journal-title":"IEEE Trans Comput"},{"issue":"3","key":"5859_CR41","doi-asserted-by":"publisher","first-page":"154","DOI":"10.1049\/ip-e.1993.0022","volume":"140","author":"M Youssef","year":"1993","unstructured":"Youssef M, Savaria Y, Kaminska B (1993) Methodology for efficiently inserting and condensing test points (cmos ics testing). IEE Proceedings-E (Computers and Digital Techniques) 140(3):154\u2013160","journal-title":"IEE Proceedings-E (Computers and Digital Techniques)"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-020-05859-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10836-020-05859-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-020-05859-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,2,2]],"date-time":"2021-02-02T00:25:32Z","timestamp":1612225532000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10836-020-05859-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2]]},"references-count":41,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2020,2]]}},"alternative-id":["5859"],"URL":"https:\/\/doi.org\/10.1007\/s10836-020-05859-4","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,2]]},"assertion":[{"value":"31 August 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 January 2020","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"3 February 2020","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}