{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T10:37:11Z","timestamp":1769164631164,"version":"3.49.0"},"reference-count":30,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/100010665","name":"H2020 Marie Sk\u0142odowska-Curie Actions","doi-asserted-by":"publisher","award":["691178"],"award-info":[{"award-number":["691178"]}],"id":[{"id":"10.13039\/100010665","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2020,6]]},"DOI":"10.1007\/s10836-020-05885-2","type":"journal-article","created":{"date-parts":[[2020,6,2]],"date-time":"2020-06-02T16:50:00Z","timestamp":1591116600000},"page":"313-326","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices"],"prefix":"10.1007","volume":"36","author":[{"given":"Lorena","family":"Anghel","sequence":"first","affiliation":[]},{"given":"Anna","family":"Bernasconi","sequence":"additional","affiliation":[]},{"given":"Valentina","family":"Ciriani","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Frontini","sequence":"additional","affiliation":[]},{"given":"Gabriella","family":"Trucco","sequence":"additional","affiliation":[]},{"given":"Ioana","family":"Vatajelu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,6,2]]},"reference":[{"issue":"8","key":"5885_CR1","doi-asserted-by":"publisher","first-page":"848","DOI":"10.1109\/TC.1972.5009040","volume":"C-21","author":"SB Akers","year":"1972","unstructured":"Akers SB (1972) A rectangular logic array. IEEE Trans Comput C-21(8):848\u2013857. https:\/\/doi.org\/10.1109\/TC.1972.5009040","journal-title":"IEEE Trans Comput"},{"key":"5885_CR2","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1016\/j.micpro.2017.08.004","volume":"54","author":"D Alexandrescu","year":"2017","unstructured":"Alexandrescu D, Altun M, Anghel L, Bernasconi A, Ciriani V, Frontini L, Tahoori M (2017) Logic synthesis and testing techniques for switching nano-crossbar arrays. Microprocess Microsyst 54:14\u201325. https:\/\/doi.org\/10.1016\/j.micpro.2017.08.004","journal-title":"Microprocess Microsyst"},{"issue":"11","key":"5885_CR3","doi-asserted-by":"publisher","first-page":"1588","DOI":"10.1109\/TC.2011.170","volume":"61","author":"M Altun","year":"2012","unstructured":"Altun M, Riedel MD (2012) Logic synthesis for switching lattices. IEEE Trans Comput 61(11):1588\u20131600. https:\/\/doi.org\/10.1109\/TC.2011.170","journal-title":"IEEE Trans Comput"},{"key":"5885_CR4","doi-asserted-by":"crossref","unstructured":"Anghel L, Bernaconi A, Ciriani V, Frontini L, Trucco G, Vatajelu I (2019) Fault mitigation of swithcing lattices under stuck-at fault model. In: Proc. of IEEE Latin American test symposium, LATS 2019, Satiago de Chile, March 2019. IEEE","DOI":"10.1109\/LATW.2019.8704615"},{"key":"5885_CR5","doi-asserted-by":"crossref","unstructured":"Bernasconi A, Ciriani V, Frontini L (2018) Testability of switching lattices in the stuck at fault model. In: Proc. IFIP\/IEEE International conference on very large scale integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018. IEEE, pp 213\u2013218","DOI":"10.1109\/VLSI-SoC.2018.8644806"},{"key":"5885_CR6","doi-asserted-by":"crossref","unstructured":"Bernasconi A, Ciriani V, Frontini L (2019) Testability of switching lattices in the cellular fault model. In: Proc. 22nd Euromicro conference on digital system design, DSD 2019, Kallithea, Greece, August 28-30, 2019. IEEE, pp 320\u2013327","DOI":"10.1109\/DSD.2019.00054"},{"issue":"7290","key":"5885_CR7","doi-asserted-by":"publisher","first-page":"873","DOI":"10.1038\/nature08940","volume":"464","author":"J Borghetti","year":"2010","unstructured":"Borghetti J, S Snider G, J Kuekes P, Yang JJ, Stewart D, Williams S (2010) Memristive switches enable stateful logic operations via material implication. Nature 464(7290):873\u2013876. https:\/\/doi.org\/10.1038\/nature08940","journal-title":"Nature"},{"key":"5885_CR8","doi-asserted-by":"crossref","unstructured":"Chen Y, Li J (2015) Fault modeling and testing of 1T1R memristor memories. In: Proc. IEEE 33rd VLSI test symposium (VTS), pp 1\u20136","DOI":"10.1109\/VTS.2015.7116247"},{"key":"5885_CR9","doi-asserted-by":"publisher","first-page":"462","DOI":"10.1088\/0957-4484\/14\/4\/311","volume":"14","author":"Y Chen","year":"2003","unstructured":"Chen Y, Jung GY, Ohlberg DAA, Li X, Stewart DR, Jeppesen JO, Nielsen KA, Stoddart JF, Williams RS (2003) Nanoscale molecular-switch crossbar circuits. Nanotechnology 14:462\u2013468. https:\/\/doi.org\/10.1088\/0957-4484\/14\/4\/311","journal-title":"Nanotechnology"},{"issue":"1","key":"5885_CR10","doi-asserted-by":"publisher","first-page":"180","DOI":"10.1109\/TC.2014.12","volume":"64","author":"C Chen","year":"2015","unstructured":"Chen C, Shih H, Wu C, Lin C, Chiu P, Sheu S, Chen FT (2015) Rram defect modeling and failure analysis based on march test and a novel squeeze-search scheme. IEEE Trans Comput 64(1):180\u2013190","journal-title":"IEEE Trans Comput"},{"key":"5885_CR11","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1016\/j.mee.2015.04.025","volume":"147","author":"R Degraeve","year":"2015","unstructured":"Degraeve R, Fantini A, Raghavan N, Goux L, Clima S, Govoreanu B, Belmonte A, Linten D, Jurczak M (2015) Causes and consequences of the stochastic aspect of filamentary RRAM. Microelectron Eng 147:171\u2013175","journal-title":"Microelectron Eng"},{"issue":"2","key":"5885_CR12","doi-asserted-by":"publisher","first-page":"719","DOI":"10.1109\/TED.2012.2231683","volume":"60","author":"Y Deng","year":"2013","unstructured":"Deng Y, Huang P, Chen B, Yang X, Gao B, Wang J, Zeng L, Du G, Kang J, yan Liu X (2013) RRAM crossbar array with cell selection device: a device and circuit interaction study. IEEE Trans Electron Dev 60(2):719\u2013726","journal-title":"IEEE Trans Electron Dev"},{"key":"5885_CR13","doi-asserted-by":"publisher","unstructured":"Gange G, S\u00f8ndergaard H, Stuckey PJ (2014) Synthesizing optimal switching lattices. ACM Transactions on Design Automation of Electronic Systems 20(1). https:\/\/doi.org\/10.1145\/2661632","DOI":"10.1145\/2661632"},{"issue":"1","key":"5885_CR14","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1109\/TC.2013.206","volume":"64","author":"S Hamdioui","year":"2015","unstructured":"Hamdioui S, Taouil M, Haron NZ (2015) Testing open defects in memristor-based memories. IEEE Trans Comput 64(1):247\u2013 259","journal-title":"IEEE Trans Comput"},{"issue":"1","key":"5885_CR15","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1109\/JPROC.2009.2032356","volume":"98","author":"M Haselman","year":"2010","unstructured":"Haselman M, Hauck S (2010) The future of integrated circuits: a survey of nanoelectronics. Proc IEEE 98 (1):11\u201338","journal-title":"Proc IEEE"},{"issue":"5545","key":"5885_CR16","doi-asserted-by":"publisher","first-page":"1313","DOI":"10.1126\/science.1066192","volume":"294","author":"Y Huang","year":"2001","unstructured":"Huang Y, Duan X, Cui Y, Lauhon LJ, Kim KH, Lieber CM (2001) Logic gates and computation from assembled nanowire building blocks. Science 294(5545):1313\u20131317","journal-title":"Science"},{"key":"5885_CR17","unstructured":"ITRS: The International Technology Roadmap for Semiconductors. In: ITRS 2011 Edition (2011)"},{"issue":"1","key":"5885_CR18","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1109\/JETCAS.2014.2374291","volume":"5","author":"W Kang","year":"2015","unstructured":"Kang W., et al. (2015) Yield and reliability improvement techniques for emerging nonvolatile stt-mram. EEE J Emerg Sel Topics Circuits Syst 5(1):28\u201339","journal-title":"EEE J Emerg Sel Topics Circuits Syst"},{"key":"5885_CR19","doi-asserted-by":"crossref","unstructured":"Kannan S, Karri R, Sinanoglu O (2013) Sneak path testing and fault modeling for multilevel memristor-based memories. In: Proc. IEEE 31st International conference on computer design (ICCD), pp 215\u2013220","DOI":"10.1109\/ICCD.2013.6657045"},{"key":"5885_CR20","doi-asserted-by":"crossref","unstructured":"Morgul MC, Tunali O, Altun M, Frontini L, Ciriani V, Vatajelu EI, Anghel L, Moritz CA, Stan MR, Alexandrescu D (2018) Integrated synthesis methodology for crossbar arrays. In: Proc. IEEE\/ACM international symposium on nanoscale architectures (NANOARCH), pp 1\u20137","DOI":"10.1145\/3232195.3232211"},{"key":"5885_CR21","doi-asserted-by":"crossref","unstructured":"Naeimi H, DeHon A (2004) A greedy algorithm for tolerating defective crosspoints in nanopla design. In: Proc. IEEE international conference on field-programmable technology , pp 49\u201356","DOI":"10.1109\/FPT.2004.1393250"},{"key":"5885_CR22","doi-asserted-by":"crossref","unstructured":"Ni L, Huang H, Liu Z, Joshi RV, Yu H (2017) Distributed in-memory computing on binary RRAM crossbar. ACM Journal on Emerging Technologies in Computing Systems 13(3)","DOI":"10.1145\/2996192"},{"issue":"6","key":"5885_CR23","doi-asserted-by":"publisher","first-page":"1165","DOI":"10.1007\/s00339-004-3149-1","volume":"80","author":"G Snider","year":"2005","unstructured":"Snider G (2005) Computing with hysteretic resistor crossbars. Appl Phys A 80(6):1165\u20131172","journal-title":"Appl Phys A"},{"issue":"6","key":"5885_CR24","doi-asserted-by":"publisher","first-page":"1183","DOI":"10.1007\/s00339-004-3154-4","volume":"80","author":"G Snider","year":"2005","unstructured":"Snider G, Kuekes P, Hogg T, Williams RS (2005) Nanoelectronic architectures. Applied Physics A 80(6):1183\u20131195","journal-title":"Applied Physics A"},{"key":"5885_CR25","doi-asserted-by":"crossref","unstructured":"Su Y, Rao W (2009) Defect-tolerant logic mapping on nanoscale crossbar architectures and yield analysis. In: Proc. 24th IEEE international symposium on defect and fault tolerance in VLSI systems, pp 322\u2013330","DOI":"10.1109\/DFT.2009.16"},{"issue":"3","key":"5885_CR26","doi-asserted-by":"publisher","first-page":"493","DOI":"10.1109\/TETC.2017.2691263","volume":"7","author":"EI Vatajelu","year":"2019","unstructured":"Vatajelu EI, Prinetto P, Taouil M, Hamdioui S (2019) Challenges and solutions in emerging memory testing. IEEE Trans Emerg Top Comput 7(3):493\u2013506","journal-title":"IEEE Trans Emerg Top Comput"},{"issue":"1","key":"5885_CR27","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1007\/s11390-016-1608-8","volume":"31","author":"L Xia","year":"2016","unstructured":"Xia L, Gu P, Li B, Tang T, Yin X, Huangfu W, Yu S, Cao Y, Wang Y, Yang H (2016) Technological exploration of RRAM crossbar array for matrix-vector multiplication. J Comput Sci Technol 31(1):3\u201319. https:\/\/doi.org\/10.1007\/s11390-016-1608-8","journal-title":"J Comput Sci Technol"},{"key":"5885_CR28","doi-asserted-by":"crossref","unstructured":"Xia L, Liu M, Ning X, Chakrabarty K, Wang Y (2017) Fault-tolerant training with on-line fault detection for RRAM-based neural computing systems. In: Proc. 54th design automation conference (DAC), pp 1\u20136","DOI":"10.1145\/3061639.3062248"},{"issue":"7333","key":"5885_CR29","doi-asserted-by":"publisher","first-page":"240","DOI":"10.1038\/nature09749","volume":"470","author":"H Yan","year":"2011","unstructured":"Yan H, Choe HS, Nam S, Hu Y, Das S, Klemic JF, Ellenbogen JC, Lieber CM (2011) Programmable nanowire circuits for nanoprocessors. Nature 470(7333):240\u2013244. https:\/\/doi.org\/10.1038\/nature09749","journal-title":"Nature"},{"key":"5885_CR30","unstructured":"Yang S (1991) Logic synthesis and optimization benchmarks user guide version 3.0. User guide, Microelectronic Center"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-020-05885-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-020-05885-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-020-05885-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,2]],"date-time":"2021-06-02T00:19:35Z","timestamp":1622593175000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-020-05885-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6]]},"references-count":30,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2020,6]]}},"alternative-id":["5885"],"URL":"https:\/\/doi.org\/10.1007\/s10836-020-05885-2","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,6]]},"assertion":[{"value":"29 July 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"8 May 2020","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 June 2020","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}