{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T11:42:20Z","timestamp":1780054940293,"version":"3.54.0"},"reference-count":77,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2021,2]]},"DOI":"10.1007\/s10836-021-05927-3","type":"journal-article","created":{"date-parts":[[2021,6,7]],"date-time":"2021-06-07T03:11:57Z","timestamp":1623035517000},"page":"25-40","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Estimating Operational Age of an Integrated Circuit"],"prefix":"10.1007","volume":"37","author":[{"given":"Prattay","family":"Chowdhury","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4819-8728","authenticated-orcid":false,"given":"Ujjwal","family":"Guin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Adit D.","family":"Singh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vishwani D.","family":"Agrawal","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2021,6,7]]},"reference":[{"key":"5927_CR1","unstructured":"Acceptability of Electronic Components Distributed in the Open Market (2017). http:\/\/www.idofea.org\/products\/118-idea-std-1010b"},{"key":"5927_CR2","unstructured":"Al Tarawneh Z (2011) The Effects of Process Variations on Performance and Robustness of Bulk CMOS and SOI Implementations of C-Elements. Ph.D. Thesis, Newcastle University"},{"key":"5927_CR3","doi-asserted-by":"crossref","unstructured":"Alam M, Chowdhury S, Tehranipoor M, Guin U (2018) Robust, Low-Cost, and Accurate Detection of Recycled ICs using Digital Signatures. In: Proc. IEEE Int. Symposium on Hardware Oriented Security and Trust (HOST)","DOI":"10.1109\/HST.2018.8383917"},{"key":"5927_CR4","doi-asserted-by":"crossref","unstructured":"Amrouch H, Mishra S, van Santen V, Mahapatra S, Henkel J (2017) Impact of BTI on dynamic and static power: From the physical to circuit level. In: Proc. IEEE International Reliability Physics Symposium (IRPS)","DOI":"10.1109\/IRPS.2017.7936352"},{"key":"5927_CR5","doi-asserted-by":"crossref","unstructured":"Asadizanjani N, Dunn N, Gattigowda S, Tehranipoor M, Forte D (2016) A database for counterfeit electronics and automatic defect detection based on image processing and machine learning. In: Proceedings of the 42nd International Symposium for Testing and Failure Analysis. Texas, USA, pp 1\u20138","DOI":"10.31399\/asm.cp.istfa2016p0580"},{"issue":"1","key":"5927_CR6","first-page":"012","volume":"787","author":"N Asadizanjani","year":"2017","unstructured":"Asadizanjani N, Tehranipoor M, Forte D (2017) Counterfeit electronics detection using image processing and machine learning. J Phys Conf Ser 787(1):012\u2013023","journal-title":"J Phys Conf Ser"},{"key":"5927_CR7","doi-asserted-by":"crossref","unstructured":"Asenov A (2007) Simulation of statistical variability in nano MOSFETs. In: Proc. IEEE Symposium on VLSI Technology, pp 86\u201387","DOI":"10.1109\/VLSIT.2007.4339737"},{"issue":"5","key":"5927_CR8","doi-asserted-by":"publisher","first-page":"1254","DOI":"10.1109\/TED.2003.813457","volume":"50","author":"A Asenov","year":"2003","unstructured":"Asenov A, Kaya S, Brown A R (2003) Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE Trans Electron Dev 50(5):1254\u20131260","journal-title":"IEEE Trans Electron Dev"},{"key":"5927_CR9","unstructured":"Brglez F (1984) On Testability Analysis of Combinational Networks. In: Proc. International Symp. Circuits and Systems, pp 221\u2013225"},{"key":"5927_CR10","unstructured":"Brglez F, Fujiwara H (June 1985) A Neutral Netlist of 10 Combinational Benchmark Circuits and a Targeted Translator in FORTRAN, Special Session on ATPG and Fault Simulation. In: Proc. 1985 IEEE Int. Symp. on Circuits and Systems (ISCAS\u201985), pp 663\u2013698. Benchmark circuit netlists are available at http:\/\/www.pld.ttu.ee\/~maksim\/benchmarks\/iscas85\/"},{"key":"5927_CR11","unstructured":"Bushnell M L, Agrawal V D (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer"},{"key":"5927_CR12","unstructured":"Certification for Counterfeit Components Avoidance Program (2011). http:\/\/www.cti-us.com\/pdf\/CCAP101Certification.pdf"},{"key":"5927_CR13","doi-asserted-by":"crossref","unstructured":"Chakravarty S, Thadikaran P J (1997) Introduction to IDDQ testing. Springer","DOI":"10.1007\/978-1-4615-6137-8"},{"key":"5927_CR14","doi-asserted-by":"crossref","unstructured":"Chandrakasan A P, Bowhill W J, Fox F (2000) Design of high-performance microprocessor circuits. Wiley-IEEE Press","DOI":"10.1109\/9780470544365"},{"key":"5927_CR15","doi-asserted-by":"crossref","unstructured":"Chowdhury P, Guin U, Singh A D, Agrawal V D (2019) Two-pattern \u0394IDDQ test for recycled IC detection. In: Proc. 32nd International Conference on VLSI Design, pp 82\u201387","DOI":"10.1109\/VLSID.2019.00033"},{"key":"5927_CR16","volume-title":"Electromigration and Electronic Device Degradation","author":"A Christou","year":"1993","unstructured":"Christou A (1993) Electromigration and Electronic Device Degradation. Wiley, New York"},{"key":"5927_CR17","unstructured":"DC Ultra: Concurrent Timing, Area, Power, and Test Optimization, https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/dc-ultra.html"},{"key":"5927_CR18","doi-asserted-by":"crossref","unstructured":"Dogan H, Forte D, Tehranipoor M M (2014) Aging analysis for recycled FPGA detection. In: Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp 171\u2013176","DOI":"10.1109\/DFT.2014.6962099"},{"key":"5927_CR19","unstructured":"Gattiker A E, Maly W (1997) Current Signatures: Application. In: Proc. International Test Conference, pp 156\u2013165"},{"key":"5927_CR20","doi-asserted-by":"crossref","unstructured":"Ghosh P, Chakraborty R S (2017) Counterfeit ic detection by image texture analysis. In: Proc. Euromicro Conference on Digital System Design (DSD). IEEE, pp 283\u2013286","DOI":"10.1109\/DSD.2017.10"},{"issue":"4","key":"5927_CR21","doi-asserted-by":"publisher","first-page":"1966","DOI":"10.1109\/TII.2018.2860953","volume":"15","author":"P Ghosh","year":"2018","unstructured":"Ghosh P, Chakraborty R S (2018) Recycled and remarked counterfeit integrated circuit detection by image processing based package texture and indent analysis. IEEE Trans Ind Inf 15(4):1966\u20131974","journal-title":"IEEE Trans Ind Inf"},{"issue":"9","key":"5927_CR22","doi-asserted-by":"publisher","first-page":"685","DOI":"10.1109\/TCS.1979.1084687","volume":"CAS-26","author":"LH Goldsein","year":"1979","unstructured":"Goldsein L H (September 1979) Controllability\/Observability Analysis of Digital Circuits. IEEE Trans Circ Syst CAS-26(9):685\u2013693","journal-title":"IEEE Trans Circ Syst"},{"issue":"1","key":"5927_CR23","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1145\/3351422.3351424","volume":"23","author":"U Guin","year":"2019","unstructured":"Guin U, Asadizanjani N, Tehranipoor M (2019) Standards for hardware security. GetMobile: Mob Comput Commun 23(1):5\u20139","journal-title":"GetMobile: Mob Comput Commun"},{"issue":"1","key":"5927_CR24","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1007\/s10836-013-5428-2","volume":"30","author":"U Guin","year":"2014","unstructured":"Guin U, DiMase D, Tehranipoor M (2014) A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment. J Electron Test 30(1):25\u201340","journal-title":"J Electron Test"},{"issue":"1","key":"5927_CR25","doi-asserted-by":"publisher","first-page":"9","DOI":"10.1007\/s10836-013-5430-8","volume":"30","author":"U Guin","year":"2014","unstructured":"Guin U, DiMase D, Tehranipoor M (2014) Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead. J Electron Test 30(1):9\u201323","journal-title":"J Electron Test"},{"issue":"4","key":"5927_CR26","doi-asserted-by":"publisher","first-page":"1233","DOI":"10.1109\/TVLSI.2015.2466551","volume":"24","author":"U Guin","year":"2016","unstructured":"Guin U, Forte D, Tehranipoor M (2016) Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling. IEEE Trans Very Large Scale Integr (VLSI) Syst 24(4):1233\u20131246","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"issue":"8","key":"5927_CR27","doi-asserted-by":"publisher","first-page":"1207","DOI":"10.1109\/JPROC.2014.2332291","volume":"102","author":"U Guin","year":"2014","unstructured":"Guin U, Huang K, DiMase D, Carulli J M, Tehranipoor M, Makris Y (2014) Counterfeit integrated circuits: A rising threat in the global semiconductor supply chain. Proc IEEE 102(8):1207\u20131228","journal-title":"Proc IEEE"},{"key":"5927_CR28","doi-asserted-by":"crossref","unstructured":"Guin U, Zhang X, Forte D, Tehranipoor M (2014) Low-cost On-Chip Structures for Combating Die and IC Recycling. In: Proc. of ACM\/IEEE Design Automation Conference","DOI":"10.1145\/2593069.2593157"},{"key":"5927_CR29","doi-asserted-by":"crossref","unstructured":"Gulati R K, Hawkins C F (eds.) (1993) IDDQ Testing of VLSI Circuits. Springer","DOI":"10.1007\/978-1-4615-3146-3"},{"key":"5927_CR30","doi-asserted-by":"crossref","unstructured":"Guo Z, Rahman M T, Tehranipoor M M, Forte D (2016) A zero-cost approach to detect recycled SoC chips using embedded SRAM. In: Proc. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp 191\u2013196","DOI":"10.1109\/HST.2016.7495581"},{"key":"5927_CR31","unstructured":"G-19A Test Laboratory Standards Development Committee (2016) Test Methods Standard; General Requirements, Suspect\/Counterfeit, Electrical, Electronic, and Electromechanical Parts. https:\/\/saemobilus.sae.org\/content\/as6171"},{"key":"5927_CR32","unstructured":"G-19CI Continuous Improvement (2009) Counterfeit Electronic Parts; Avoidance, Detection, Mitigation, and Disposition. https:\/\/saemobilus.sae.org\/content\/as5553"},{"key":"5927_CR33","doi-asserted-by":"crossref","unstructured":"He K, Huang X, Tan S X D (2015) EM-based on-chip aging sensor for detection and prevention of counterfeit and recycled ICs. In: Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp 146\u2013151","DOI":"10.1109\/ICCAD.2015.7372562"},{"key":"5927_CR34","doi-asserted-by":"crossref","unstructured":"Hofmann K, Reisinger H, Ermisch K, Schl\u00fcnder C, Gustin W, Pompl T, Georgakos G, von Arnim K, Hatsch J, Kodytek T et al (2010) Highly accurate product-level aging monitoring in 40nm CMOS. In: Proc. Symposium on VLSI Technology, pp 27\u201328","DOI":"10.1109\/VLSIT.2010.5556134"},{"key":"5927_CR35","doi-asserted-by":"crossref","unstructured":"Huang K, Carulli JM, Makris Y (2012) Parametric counterfeit IC detection via Support Vector Machines. In: Proc. International Symposium on Fault and Defect Tolerance in VLSI Systems, pp 7\u201312","DOI":"10.1109\/DFT.2012.6378191"},{"key":"5927_CR36","unstructured":"IHS iSuppli (2011) Top 5 Most Counterfeited Parts Represent a $169 Billion Potential Challenge for Global Semiconductor Market. http:\/\/press.ihs.com\/press-release\/design-supply-chain\/top-5-most-counterfeited-parts-represent-169-billion-potential-cha"},{"issue":"4","key":"5927_CR37","doi-asserted-by":"publisher","first-page":"817","DOI":"10.1109\/JSSC.2010.2040125","volume":"45","author":"J Keane","year":"2010","unstructured":"Keane J, Wang X, Persaud D, Kim C H (2010) An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB. IEEE J Solid-State Circ 45(4):817\u2013829","journal-title":"IEEE J Solid-State Circ"},{"key":"5927_CR38","doi-asserted-by":"crossref","unstructured":"Kiamehr S, Amouri A, Tahoori M B (2011) Investigation of NBTI and PBTI induced aging in different LUT implementations. In: Proc. International Conference on Field-Programmable Technology, pp 1\u20138","DOI":"10.1109\/FPT.2011.6132704"},{"issue":"12","key":"5927_CR39","doi-asserted-by":"publisher","first-page":"68","DOI":"10.1109\/MC.2003.1250885","volume":"36","author":"NS Kim","year":"2003","unstructured":"Kim N S, Austin T, Baauw D, Mudge T, Flautner K, Hu J S, Irwin M J, Kandemir M, Narayanan V (2003) Leakage current: Moore\u2019s law meets static power. Computer 36(12):68\u201375","journal-title":"Computer"},{"issue":"4","key":"5927_CR40","doi-asserted-by":"publisher","first-page":"874","DOI":"10.1109\/JSSC.2008.917502","volume":"43","author":"T-H Kim","year":"2008","unstructured":"Kim T-H, Persaud R, Kim CH (2008) Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits. IEEE J Solid-State Circ 43(4):874\u2013880","journal-title":"IEEE J Solid-State Circ"},{"issue":"8","key":"5927_CR41","doi-asserted-by":"publisher","first-page":"2197","DOI":"10.1109\/TED.2011.2121913","volume":"58","author":"KJ Kuhn","year":"2011","unstructured":"Kuhn K J, Giles M D, Becher D, Kolar P, Kornfeld A, Kotlyar R, Ma S T, Maheshwari A, Mudanai S (2011) Process Technology Variation. IEEE Trans Electron Dev 58(8):2197\u20132208","journal-title":"IEEE Trans Electron Dev"},{"key":"5927_CR42","unstructured":"Kuhn K, Kenyon C, Kornfeld A, Liu M, Maheshwari A, Shih W-, Sivakumar S, Taylor G, VanDerVoorn P, Zawadzki K (2008) Managing Process Variation in Intel\u2019s 45nm CMOS Technology. Intel Technol J 12(2)"},{"key":"5927_CR43","unstructured":"Maxwell P, O\u2019Neill P, Aitken R, Dudley R, Jaarsma N, Quach M, Wiseman D (1999) Current Ratios: A Self-scaling Technique for Production IDDQ Testing. In: Proc. International Test Conference, pp 738\u2013746"},{"key":"5927_CR44","doi-asserted-by":"crossref","unstructured":"Miller M, Meraglia J, Hayward J (2012) Traceability in the age of globalization: A proposal for a marking protocol to assure authenticity of electronic parts. In: Proc. SAE Aerospace Electronics and Avionics Systems Conference","DOI":"10.4271\/2012-01-2104"},{"issue":"6","key":"5927_CR45","doi-asserted-by":"publisher","first-page":"668","DOI":"10.1109\/T-C.1975.224279","volume":"C-24","author":"KP Parker","year":"1975","unstructured":"Parker K P, McCluskey E J (June 1975) Probabilistic Treatment of General Combinational Networks. IEEE Trans Comput C-24(6):668\u2013670","journal-title":"IEEE Trans Comput"},{"key":"5927_CR46","unstructured":"Physical Verification: Using IC Validator, https:\/\/www.synopsys.com\/implementation-and-signoff\/physical-verification.html"},{"key":"5927_CR47","doi-asserted-by":"crossref","unstructured":"Powell T J, Pair J, John M S, Counce D (2000) Delta Iddq for Testing Reliability. In: Proc. 18th IEEE VLSI Test Symposium (VTS), Montreal, pp 439\u2013443","DOI":"10.1109\/VTEST.2000.843876"},{"key":"5927_CR48","unstructured":"Predictive Technology Model (PTM), http:\/\/ptm.asu.edu\/"},{"issue":"4","key":"5927_CR49","doi-asserted-by":"publisher","first-page":"544","DOI":"10.1109\/5.843000","volume":"88","author":"R Rajsuman","year":"2000","unstructured":"Rajsuman R (2000) Iddq testing for CMOS VLSI. Proc IEEE 88(4):544\u2013568","journal-title":"Proc IEEE"},{"issue":"11","key":"5927_CR50","doi-asserted-by":"publisher","first-page":"1245","DOI":"10.1109\/TVLSI.2007.904128","volume":"15","author":"L Rao","year":"2007","unstructured":"Rao L, Bushnell M L, Agrawal V D (November 2007) Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. IEEE Trans Very Large Scale Integr (VLSI) Syst 15(11):1245\u20131255","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"5927_CR51","doi-asserted-by":"crossref","unstructured":"Rao R, Srivastava A, Blaauw D, Sylvester D (2003) Statistical estimation of leakage current considering inter-and intra-die process variation. In: Proc. International Symposium on Low Power Electronics and Design, pp 84\u201389","DOI":"10.1145\/871506.871530"},{"issue":"1","key":"5927_CR52","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1016\/j.microrel.2004.05.023","volume":"25","author":"V Reddy","year":"2005","unstructured":"Reddy V, Krishnan A T, Marshall A, Rodriguez J, Natarajan S, Rost T, Krishnan S (2005) Impact of negative bias temperature instability on digital circuit reliability. Microelectron Reliab 25 (1):31\u201338","journal-title":"Microelectron Reliab"},{"issue":"2","key":"5927_CR53","doi-asserted-by":"publisher","first-page":"159","DOI":"10.1145\/989995.989997","volume":"9","author":"SS Sabade","year":"2004","unstructured":"Sabade S S, Walker D M H (April 2004) IDDX-based Test Methods: A Survey. ACM Trans Des Autom Electron Syst 9(2):159\u2013198","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"5927_CR54","unstructured":"SAE Counterfeit Defect Coverage Tool, http:\/\/cdctool.sae.org\/"},{"key":"5927_CR55","doi-asserted-by":"crossref","unstructured":"Saneyoshi E, Nose K, Mizuno M (2010) A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp 192\u2013193","DOI":"10.1109\/ISSCC.2010.5433994"},{"issue":"1","key":"5927_CR56","doi-asserted-by":"publisher","first-page":"79","DOI":"10.1109\/TC.1984.5009315","volume":"C-33","author":"J Savir","year":"1984","unstructured":"Savir J, Ditlow G S, Bardell P H (January 1984) Random Pattern Testability. IEEE Trans Comput C-33(1):79\u201390","journal-title":"IEEE Trans Comput"},{"issue":"6","key":"5927_CR57","doi-asserted-by":"publisher","first-page":"841","DOI":"10.1016\/j.microrel.2006.10.006","volume":"47","author":"DK Schroder","year":"2007","unstructured":"Schroder D K (2007) Negative bias temperature instability: What do we understand?. Microelectron Reliab 47(6):841\u2013852","journal-title":"Microelectron Reliab"},{"issue":"1","key":"5927_CR58","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1063\/1.1567461","volume":"94","author":"DK Schroder","year":"2003","unstructured":"Schroder D K, Babcock J A (2003) Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing. J Appl Phys 94(1):1\u201318","journal-title":"J Appl Phys"},{"key":"5927_CR59","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1016\/0167-9260(89)90059-X","volume":"7","author":"SC Seth","year":"1989","unstructured":"Seth S C, Agrawal V D (1989) A New Model for Computation of Probabilistic Testability in Combinational Circuits. Integr Vlsi J 7:49\u201375","journal-title":"Integr Vlsi J"},{"key":"5927_CR60","doi-asserted-by":"crossref","unstructured":"Shahbazmohamadi S, Forte D, Tehranipoor M (2014) Advanced physical inspection methods for counterfeit ic detection. In: ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis. ASM International , pp 55","DOI":"10.31399\/asm.cp.istfa2014p0055"},{"issue":"7","key":"5927_CR61","doi-asserted-by":"publisher","first-page":"1538","DOI":"10.1109\/TED.2009.2020321","volume":"56","author":"C Shin","year":"2009","unstructured":"Shin C, Sun X, Liu T-J K (2009) Study of random-dopant-fluctuation (RDF) effects for the trigate bulk MOSFET. IEEE Trans Electron Dev 56(7):1538\u20131542","journal-title":"IEEE Trans Electron Dev"},{"issue":"9-11","key":"5927_CR62","doi-asserted-by":"publisher","first-page":"1199","DOI":"10.1016\/j.microrel.2010.07.017","volume":"50","author":"JH Stathis","year":"2010","unstructured":"Stathis J H, Wang M, Zhao K (2010) Reliability of advanced high-k\/metal-gate n-FET devices. Microelectron Reliab 50(9-11):1199\u20131202","journal-title":"Microelectron Reliab"},{"key":"5927_CR63","unstructured":"Synopsys 32\/28nm Generic Library for Teaching IC Design, https:\/\/www.synopsys.com\/community\/university-program\/teaching-resources.html"},{"issue":"6","key":"5927_CR64","doi-asserted-by":"publisher","first-page":"675","DOI":"10.1109\/T-ED.1983.21188","volume":"30","author":"E Takeda","year":"1983","unstructured":"Takeda E, Nakagome Y, Kume H, Suzuki N, Asai SHOJIRO (1983) Comparison of characteristics of n-channel and p-channel MOSFET\u2019s for VLSI\u2019s. IEEE Trans Electron Dev 30(6):675\u2013680","journal-title":"IEEE Trans Electron Dev"},{"key":"5927_CR65","doi-asserted-by":"crossref","unstructured":"Tehranipoor M M, Guin U, Forte D (2015) Counterfeit Integrated Circuits: Detection and Avoidance. Springer","DOI":"10.1007\/978-3-319-11824-6"},{"key":"5927_CR66","doi-asserted-by":"crossref","unstructured":"Thibeault C (1997) A Novel Probabilistic Approach for IC Diagnosis Based on Differential Quiescent Current Signatures. In: Proc. 15th IEEE VLSI Test Symposium, pp 80\u201385","DOI":"10.1109\/VTEST.1997.599445"},{"key":"5927_CR67","unstructured":"Tudor B, Wang J, Liu W, Elhak H (2011) MOS device aging analysis with HSPICE and Customsim. Synopsys, White Paper"},{"key":"5927_CR68","unstructured":"VCS: Industry\u2019s Highest Performance Simulation Solution, https:\/\/www.synopsys.com\/verification\/simulation\/vcs.html"},{"key":"5927_CR69","doi-asserted-by":"crossref","unstructured":"Wang W, Reddy V, Yang B, Balakrishnan V, Krishnan S, Cao Y (2008) Statistical prediction of circuit aging under process variations. In: Proc. Custom Integrated Circuits Conference (CICC), pp 13\u201316","DOI":"10.1109\/CICC.2008.4672007"},{"key":"5927_CR70","unstructured":"Weste NHE, Harris D (2015) CMOS VLSI design: a circuits and systems perspective. Pearson Education India"},{"issue":"4","key":"5927_CR71","doi-asserted-by":"publisher","first-page":"1027","DOI":"10.1109\/TED.2003.812504","volume":"50","author":"Y-C Yeo","year":"2003","unstructured":"Yeo Y-C, King T-J, Hu C (2003) MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Trans Electron Dev 50(4):1027\u20131035","journal-title":"IEEE Trans Electron Dev"},{"key":"5927_CR72","doi-asserted-by":"crossref","unstructured":"Zafar S, Kim Y, Narayanan V, Cabral C, Paruchuri V, Doris B, Stathis J, Callegari A, Chudzik M (2006) A comparative study of NBTI and PBTI (charge trapping) in SiO2\/HfO2 stacks with FUSI, TiN, Re gates. In: Symposium on VLSI Technology, Digest of Technical Papers, pp 23\u201325","DOI":"10.1109\/VLSIT.2006.1705198"},{"issue":"5","key":"5927_CR73","doi-asserted-by":"publisher","first-page":"1016","DOI":"10.1109\/TVLSI.2013.2264063","volume":"22","author":"X Zhang","year":"2014","unstructured":"Zhang X, Tehranipoor M (2014) Design of on-chip lightweight sensors for effective detection of recycled ICs. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(5):1016\u20131029","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"5927_CR74","doi-asserted-by":"crossref","unstructured":"Zhang X, Tuzzio N, Tehranipoor M (2012) Identification of recovered ICs using fingerprints from a light-weight on-chip sensor. In: Proc. IEEE-ACM Design Automation Conference","DOI":"10.1145\/2228360.2228486"},{"key":"5927_CR75","doi-asserted-by":"crossref","unstructured":"Zhang X, Xiao K, Tehranipoor M (2012) Path-delay fingerprinting for identification of recovered ics. In: Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp 13\u201318","DOI":"10.1109\/DFT.2012.6378192"},{"key":"5927_CR76","doi-asserted-by":"crossref","unstructured":"Zheng Y, Basak A, Bhunia S (2014) CACI: Dynamic current analysis towards robust recycled chip identification. In: Proceedings of the 51st Annual Design Automation Conference, pp 1\u20136","DOI":"10.1145\/2593069.2593102"},{"issue":"5","key":"5927_CR77","doi-asserted-by":"publisher","first-page":"831","DOI":"10.1109\/TVLSI.2014.2326556","volume":"23","author":"Y Zheng","year":"2015","unstructured":"Zheng Y, Wang X, Bhunia S (2015) SACCI: Scan-based characterization through clock phase sweep for counterfeit chip detection. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(5):831\u2013841","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05927-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-021-05927-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05927-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,11]],"date-time":"2021-06-11T06:47:50Z","timestamp":1623394070000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-021-05927-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2]]},"references-count":77,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2021,2]]}},"alternative-id":["5927"],"URL":"https:\/\/doi.org\/10.1007\/s10836-021-05927-3","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,2]]},"assertion":[{"value":"27 April 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 January 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"7 June 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}