{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T02:28:30Z","timestamp":1781836110438,"version":"3.54.5"},"reference-count":82,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2021,2]]},"DOI":"10.1007\/s10836-021-05929-1","type":"journal-article","created":{"date-parts":[[2021,2,23]],"date-time":"2021-02-23T12:03:33Z","timestamp":1614081813000},"page":"7-24","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":26,"title":["Pre-Silicon Verification Using Multi-FPGA Platforms: A Review"],"prefix":"10.1007","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5220-4908","authenticated-orcid":false,"given":"Umer","family":"Farooq","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2021,2,23]]},"reference":[{"key":"5929_CR1","unstructured":"Aldec: The design verification company (2020) https:\/\/www.aldec.com\/en"},{"key":"5929_CR2","doi-asserted-by":"crossref","unstructured":"Alpert CJ, Chan T, Huang D, Kahng A, Markov I, Mulet P, and Yan K (1997) \u201cFaster Minimization of Linear Wirelength for Global Placement,\u201d ACM Symposium on Physical Design, pp. 4\u201311","DOI":"10.1145\/267665.267670"},{"key":"5929_CR3","doi-asserted-by":"crossref","unstructured":"Alpert CJ, Hagen LW, and Kahng AB (1997) \u201cMultilevel Circuit Partitioning,\u201d Design Automation Conference, pp. 530\u2013533","DOI":"10.1145\/266021.266275"},{"key":"5929_CR4","unstructured":"Altera (2020) http:\/\/www.altera.com"},{"key":"5929_CR5","unstructured":"AMD (2007) http:\/\/techreport.com\/news\/13721\/chip-problem-limits-supply-of-quad-core-opterons"},{"key":"5929_CR6","unstructured":"Auspy (2020) https:\/\/www.mentor.com\/products\/fv\/aupsy"},{"key":"5929_CR7","unstructured":"Avnet: Simulation and verification services (2020) http:\/\/www.avid-tech.com\/services\/pcb-design-and-simulation\/simulation-and-verification-services\/"},{"issue":"6","key":"5929_CR8","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/43.640619","volume":"16","author":"J Babb","year":"1997","unstructured":"Babb J, Tessier R, Dahl M, Hanono S, Hoki D, Agarwal A (1997) Logic emulation with virtual wires. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 16(6):609\u2013626","journal-title":"Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on"},{"key":"5929_CR9","unstructured":"Berkeley, ABC: A System for Sequential Synthesis and Verification (2007) http:\/\/www.eecs.berkeley.edu\/alanmi\/abc\/"},{"key":"5929_CR10","doi-asserted-by":"crossref","unstructured":"Bui TN, Moon BR (1994) \u201cA fast and stable hybrid genetic algorithm for the ratio-cut partitioning problem on hypergraphs,\u201d in 31st Design Automation Conference. IEEE 664\u2013669","DOI":"10.1145\/196244.196607"},{"key":"5929_CR11","unstructured":"Cadence (2020) https:\/\/www.cadence.com\/en_us\/home\/tools\/system-design-and-verification\/simulation-and-testbench-verification\/incisive-enterprise-simulator.html"},{"key":"5929_CR12","unstructured":"Cadence protium platform (2020) https:\/\/www.cadence.com\/en_US\/home\/tools\/system-design-and-verification\/fpga-basedprototyping\/protium-s1-fpga-based-prototyping-platform.html"},{"key":"5929_CR13","unstructured":"Cadence virtual system platform (2020) https:\/\/www.cadence.com\/en_US\/home\/tools\/system-design-and-verification\/software-driven-verification\/virtual-system-platform.html"},{"key":"5929_CR14","unstructured":"Certify partitioning tool by synopsys (2017) http:\/\/www.synopsys.com\/Prototyping\/FPGABasedPrototyping\/Pages\/Certify.aspx"},{"issue":"9","key":"5929_CR15","doi-asserted-by":"publisher","first-page":"1088","DOI":"10.1109\/43.310898","volume":"13","author":"PK Chan","year":"1994","unstructured":"Chan PK, Schlag MD, Zien JY (1994) Spectral k-way ratio-cut partitioning and clustering. IEEE Transactions on computer-aided design of integrated circuits and systems 13(9):1088\u20131096","journal-title":"IEEE Transactions on computer-aided design of integrated circuits and systems"},{"key":"5929_CR16","unstructured":"DiniGroup (2020) http:\/\/www.dinigroup.com\/"},{"key":"5929_CR17","doi-asserted-by":"crossref","unstructured":"Dunlop A, and Kernighan B (1985) \u201cA Procedure for Placement of Standard-cell VLSI Circuits,\u201d IEEE Transactions on CAD, pp. 92\u201398","DOI":"10.1109\/TCAD.1985.1270101"},{"key":"5929_CR18","doi-asserted-by":"crossref","unstructured":"Farooq U, Baig I, and Alzahrani BA (2018) \u201cAn efficient inter-fpga routing exploration environment for multi-fpga systems,\u201d IEEE Access, vol. 6, pp. 56. 301\u201356-310","DOI":"10.1109\/ACCESS.2018.2873041"},{"key":"5929_CR19","doi-asserted-by":"crossref","unstructured":"Farooq U, Chotin-Avot R, Azeem M, Ravoson M, and Mehrez H (2018) \u201cNovel architectural space exploration environment for multi-fpga based prototyping systems,\u201d Microprocessors and Microsystems, vol. 56, pp. 169 \u2013 183. [Online]. Available: http:\/\/www.sciencedirect.com\/science\/article\/pii\/S0141933117300091","DOI":"10.1016\/j.micpro.2017.12.006"},{"issue":"1\u20132","key":"5929_CR20","doi-asserted-by":"publisher","first-page":"117","DOI":"10.1007\/s10617-018-9207-2","volume":"22","author":"U Farooq","year":"2018","unstructured":"Farooq U, Mehrez H, Bhatti MK (2018) Inter-fpga interconnect topologies exploration for multi-fpga systems. Design Automation for Embedded Systems 22(1\u20132):117\u2013140","journal-title":"Design Automation for Embedded Systems"},{"key":"5929_CR21","doi-asserted-by":"crossref","unstructured":"Farooq U, Parvez H, Mehrez H, and Marrakchi Z (2011) Exploration of heterogeneous fpga architectures, Int. J. Reconfig. Comput., vol. 2011, pp. 2:1\u20132:18, Jan. 2011. [Online]. Available: http:\/\/dx.doi.org\/10.1155\/2011\/121404","DOI":"10.1155\/2011\/121404"},{"issue":"8","key":"5929_CR22","doi-asserted-by":"publisher","first-page":"588","DOI":"10.1016\/j.micpro.2012.06.012","volume":"36","author":"U Farooq","year":"2012","unstructured":"Farooq U, Parvez H, Mehrez H, Marrakchi Z (2012) A new heterogeneous tree-based application specific fpga and its comparison with mesh-based application specific fpga. Microprocessors and Microsystems 36(8):588\u2013605","journal-title":"Microprocessors and Microsystems"},{"key":"5929_CR23","doi-asserted-by":"crossref","unstructured":"Fiduccia CM, and Mattheyeses RM (1982) \u201cA Linear-time Heuristic for Improving Network Partitions,\u201d Design Automation Conference, pp. 175\u2013181","DOI":"10.1109\/DAC.1982.1585498"},{"key":"5929_CR24","unstructured":"Flexras (2020) https:\/\/www.mentor.com\/products\/fv\/flexras"},{"key":"5929_CR25","volume-title":"Computers and Intractability; A Guide to the Theory of NP-Completeness","author":"MR Garey","year":"1990","unstructured":"Garey MR, Johnson DS (1990) Computers and Intractability; A Guide to the Theory of NP-Completeness. W. H. Freeman & Co., New York, NY, USA"},{"issue":"6","key":"5929_CR26","doi-asserted-by":"publisher","first-page":"81","DOI":"10.3390\/electronics7060081","volume":"7","author":"T Grimm","year":"2018","unstructured":"Grimm T, Lettnin D, H\u00fcbner M (2018) A survey on formal verification techniques for safety-critical systems-on-chip. Electronics 7(6):81","journal-title":"Electronics"},{"key":"5929_CR27","doi-asserted-by":"crossref","unstructured":"Guo X, Dutta RG, Jin Y, Farahmandi F, and Mishra P (2015) Pre-silicon security verification and validation: A formal perspective, in Proceedings of the 52nd Annual Design Automation Conference, pp. 1\u20136","DOI":"10.1145\/2744769.2747939"},{"issue":"9","key":"5929_CR28","doi-asserted-by":"publisher","first-page":"1074","DOI":"10.1109\/43.159993","volume":"11","author":"L Hagen","year":"1992","unstructured":"Hagen L, Kahng AB (1992) New spectral methods for ratio cut partitioning and clustering. IEEE transactions on computer-aided design of integrated circuits and systems 11(9):1074\u20131085","journal-title":"IEEE transactions on computer-aided design of integrated circuits and systems"},{"key":"5929_CR29","unstructured":"Haps multi-fpga board by synopsys (2020) http:\/\/www.synopsys.com\/Prototyping\/FPGABasedPrototyping\/Pages\/HAPS.aspx"},{"key":"5929_CR30","unstructured":"Haps protocompiler by synopsys (2020) http:\/\/www.synopsys.com\/Prototyping\/FPGABasedPrototyping\/Pages\/protocompiler.aspx"},{"key":"5929_CR31","doi-asserted-by":"crossref","unstructured":"Hauck S, and Borriello G (1995) \u201cLogic partition orderings for multi-fpga systems,\u201d in Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, pp. 32\u201338","DOI":"10.1145\/201310.201315"},{"key":"5929_CR32","volume-title":"Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation","author":"S Hauck","year":"2007","unstructured":"Hauck S, DeHon A (2007) Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA"},{"key":"5929_CR33","unstructured":"Hennessy P, (2011) Computer Architecture: A Quantitative Approach, 5th; ed. Morgan Kauffman"},{"key":"5929_CR34","unstructured":"Huang CY, Yin YF, Hsu CJ, Huang TB, Chang TM (2011) \u201cSoc hw\/sw verification and validation,\u201d in 16th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE 2011:297\u2013300"},{"key":"5929_CR35","doi-asserted-by":"crossref","unstructured":"Huang D, and Kahng A (1997) \u201cPartitioning-based Standard-cell Global Placement with an Exact Objective,\u201d ACM Symposium on Physical Design, pp. 18\u201325","DOI":"10.1145\/267665.267674"},{"key":"5929_CR36","unstructured":"Ic insights (2018) https:\/\/www.icinsights.com\/news\/bulletins\/Automotive-And-IoT-Will-Drive-IC-Growth-Through-2021\/"},{"key":"5929_CR37","doi-asserted-by":"crossref","unstructured":"Inagi M, Takashima Y, and Nakamura Y (2009) \u201cGlobally optimal time-multiplexing in inter-fpga connections for accelerating multi-fpga systems,\u201d in Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on, pp. 212\u2013217","DOI":"10.1109\/FPL.2009.5272309"},{"key":"5929_CR38","unstructured":"Intel, Quartus prime, https:\/\/www.intel.com\/content\/www\/us\/en\/software\/programmable\/quartus-prime\/overview.html"},{"key":"5929_CR39","doi-asserted-by":"crossref","unstructured":"Karypis G, Aggarwal R, Kumar V, and Shekhar S (1997) \u201cMultilevel Hypergraph Partitioning: Application in VLSI Design,\u201d Design Automation Conference, pp. 526\u2013529","DOI":"10.1145\/266021.266273"},{"key":"5929_CR40","doi-asserted-by":"crossref","unstructured":"Karypis G, and Kumar V (1999) \u201cMultilevel k-way Hypergraph Partitioning,\u201d Design automation conference","DOI":"10.1145\/309847.309954"},{"issue":"2","key":"5929_CR41","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1145\/307988.307989","volume":"4","author":"C Kern","year":"1999","unstructured":"Kern C, Greenstreet MR (1999) Formal verification in hardware design: a survey. ACM Transactions on Design Automation of Electronic Systems (TODAES) 4(2):123\u2013193","journal-title":"ACM Transactions on Design Automation of Electronic Systems (TODAES)"},{"key":"5929_CR42","doi-asserted-by":"publisher","first-page":"291","DOI":"10.1002\/j.1538-7305.1970.tb01770.x","volume":"49","author":"B Kernighan","year":"1970","unstructured":"Kernighan B, Lin S (1970) An Efficient Heuristic Procedure for Partitioning Graphs. Bell System Tech. Journal 49:291\u2013307","journal-title":"Bell System Tech. Journal"},{"key":"5929_CR43","doi-asserted-by":"publisher","first-page":"671","DOI":"10.1126\/science.220.4598.671","volume":"220","author":"S Kirkpatrick","year":"1983","unstructured":"Kirkpatrick S, Gelatt CD, Vecchi MP (1983) Optimization by Simulated Annealing. Science 220:671\u2013680","journal-title":"Science"},{"issue":"5","key":"5929_CR44","doi-asserted-by":"publisher","first-page":"438","DOI":"10.1109\/TC.1984.1676460","volume":"33","author":"B Krishnamurthy","year":"1984","unstructured":"Krishnamurthy B (1984) An improved min-cut algonthm for partitioning vlsi networks. IEEE Transactions on computers 33(5):438\u2013446","journal-title":"IEEE Transactions on computers"},{"key":"5929_CR45","unstructured":"Krupnova H (2005) \u201cMapping multi-million gate socs on fpgas: industrial methodology and experience,\u201d in Design, Automation and Test in Europe Conference and Exhibition, Proceedings, vol. 2, Feb 2004, pp. 1236\u20131241 Vol.2"},{"key":"5929_CR46","doi-asserted-by":"crossref","unstructured":"Kuon JRI (2010) Quantifying and Exploring the Gap Between FPGAs and ASICs, Springer, Ed. Springer US, vol. 1","DOI":"10.1007\/978-1-4419-0739-4_1"},{"key":"5929_CR47","doi-asserted-by":"crossref","unstructured":"Kulmala A, Salminen E, and H\u00e4m\u00e4l\u00e4inen TD (2007) \u201cEvaluating large system-on-chip on multi-fpga platform,\u201d in International Workshop on Embedded Computer Systems. Springer, pp. 179\u2013189","DOI":"10.1007\/978-3-540-73625-7_20"},{"key":"5929_CR48","unstructured":"M. Graphics (2018) The weather report: 2018 study on ic\/asic verification trends, https:\/\/semiengineering.com\/the-weather-report-2018-study-on-ic-asic-verification-trends\/"},{"key":"5929_CR49","unstructured":"M. Graphics (2020) https:\/\/www.mentor.com\/products\/fv\/modelsim\/"},{"key":"5929_CR50","unstructured":"Marrakchi Z, Mrabet H, and Mehrez H (2005) \u201cHierarchical FPGA Clustering to Improve Routability,\u201d Conference on Ph.D Research in Microelectronics and Electronics, PRIME"},{"key":"5929_CR51","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.6","volume-title":"A new Multilevel Hierarchical MFPGA and its suitable configuration tools","author":"Z Marrakchi","year":"2006","unstructured":"Marrakchi Z, Mrabet H, Mehrez H (2006) A new Multilevel Hierarchical MFPGA and its suitable configuration tools. Proc, ISVLSI, Karlsruhe, Germany"},{"key":"5929_CR52","doi-asserted-by":"crossref","unstructured":"McMurchie L, Ebeling C (1995) \u201cPathfinder: A negotiation-based performance-driven router for fpgas,\u201d in ACM International Symposium on Field-Programmable Gate Arrays. ACM Press, New York, NY, USA, pp. 111\u2013117","DOI":"10.1109\/FPGA.1995.242049"},{"key":"5929_CR53","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-59418-7","volume-title":"Asic\/soc functional design verification","author":"AB Mehta","year":"2018","unstructured":"Mehta AB (2018) Asic\/soc functional design verification. Publ, Springer"},{"key":"5929_CR54","unstructured":"Mentor graphics vista (2020) https:\/\/www.mentor.com\/products\/fv\/vista"},{"key":"5929_CR55","doi-asserted-by":"crossref","unstructured":"Patil S, Scholten S, Tao M, Al-Asaad H, Survey of memory, timing, and power management verification methods for multi-core processors, in, (2019) IEEE 10th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON). IEEE 2019:0110\u20130119","DOI":"10.1109\/IEMCON.2019.8936198"},{"key":"5929_CR56","unstructured":"Pentium (1994) https:\/\/en.wikipedia.org\/wiki\/pentium_fdiv_bug"},{"key":"5929_CR57","unstructured":"ProDesign (2020) https:\/\/www.profpga.com\/"},{"key":"5929_CR58","unstructured":"S2c multi-fpga prototyping (2020) http:\/\/www.s2cinc.com\/design-classification\/multi-fpga-prototyping"},{"key":"5929_CR59","unstructured":"Santarini M (2005) Asic prototyping: Make versus buy. EDN 11"},{"key":"5929_CR60","doi-asserted-by":"crossref","unstructured":"Sechen C, and Sangiovanni-Vincentelli A (1985) \u201cThe Timberwolf Placement and Routing Package,\u201d JSSC, pp. 510\u2013522","DOI":"10.1109\/JSSC.1985.1052337"},{"key":"5929_CR61","doi-asserted-by":"crossref","unstructured":"Selvakkumaran N, Ranjan A, Raje S, and Karypis G (2004) \u201cMulti-resource aware partitioning algorithms for fpgas with heterogeneous resources,\u201d in Proceedings of the 41st annual Design Automation Conference, pp. 741\u2013746","DOI":"10.1145\/996566.996768"},{"key":"5929_CR62","unstructured":"Series CP (2020) http:\/\/www.cadence.com\/products\/sd\/palladium_xp_series\/pages\/default.aspx"},{"key":"5929_CR63","unstructured":"Sigenics: Custom asic calculator (2017) http:\/\/www.sigenics.com\/page\/custom-asic-cost-calculator"},{"key":"5929_CR64","doi-asserted-by":"crossref","unstructured":"Sigl G, Doll K, and Johannes F (1991) \u201cAnalytical Placement: A Linear or a Quadratic Objective Function?\u201d Design Automation Conference, pp. 427\u2013432","DOI":"10.1145\/127601.127707"},{"key":"5929_CR65","doi-asserted-by":"crossref","unstructured":"Song X, Hung WN, Mishchenko A, Chrzanowska-Jeske M, Kennings A, and Coppola A (2003) \u201cBoard-level multiterminal net assignment for the partial cross-bar architecture,\u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(3):511\u2013514","DOI":"10.1109\/TVLSI.2003.812322"},{"key":"5929_CR66","unstructured":"Synopsys, Synplify premier (2020) https:\/\/www.synopsys.com\/implementation-and-signoff\/fpga-based-design\/synplify-pro.html"},{"key":"5929_CR67","unstructured":"Synopsys virtualizer (2020) https:\/\/www.synopsys.com\/verification\/virtual-prototyping\/virtualizer.html"},{"key":"5929_CR68","doi-asserted-by":"crossref","unstructured":"Tang Q, Mehrez H, and Tuna M (2013) \u201cRouting algorithm for multi-fpga based systems using multi-point physical tracks,\u201d in Rapid System Prototyping (RSP), 2013 International Symposium on, pp. 2\u20138","DOI":"10.1109\/RSP.2013.6683951"},{"key":"5929_CR69","doi-asserted-by":"crossref","unstructured":"Tang Q, Tuna M, Mehrez H, \u201crformance comparison between multi-fpga prototyping platforms: Hardwired off-the-shelf, cabling, and custom,\u201d in, (2014) IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines. IEEE 2014:125\u2013132","DOI":"10.1109\/FCCM.2014.44"},{"key":"5929_CR70","doi-asserted-by":"crossref","unstructured":"Turki M, Marrakchi Z, Mehrez H, and Abid M (2013) Reconfigurable Computing: Architectures, Tools and Applications: 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013, ch. Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform, pp. 210\u2013217","DOI":"10.1007\/978-3-642-36812-7_20"},{"key":"5929_CR71","doi-asserted-by":"crossref","unstructured":"Turki M, Mehrez H, Marrakchi Z, and Abid M (2013) \u201cPartitioning constraints and signal routing approach for multi-fpga prototyping platform,\u201d in 2013 International Symposium on System on Chip (SoC), pp. 1\u20134","DOI":"10.1109\/ISSoC.2013.6675273"},{"key":"5929_CR72","doi-asserted-by":"crossref","unstructured":"Varghese J, Butts M, and Batcheller J (1993) \u201cAn efficient logic emulation system,\u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, pp. 171\u2013174","DOI":"10.1109\/92.238418"},{"key":"5929_CR73","unstructured":"Vcs: A functional veriifcation solution by synopsys (2020) http:\/\/www.synopsys.com\/Tools\/Verification\/FunctionalVerification\/Pages\/VCS.aspx"},{"key":"5929_CR74","unstructured":"Veloce MG (2020) https:\/\/www.mentor.com\/products\/fv\/emulation-systems\/"},{"key":"5929_CR75","unstructured":"VERIFIC (2020) https:\/\/www.verific.com\/"},{"issue":"2","key":"5929_CR76","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/54.82034","volume":"8","author":"S Walters","year":"1991","unstructured":"Walters S (1991) Computer-aided prototyping for asic-based systems. IEEE Design & Test of Computers 8(2):4\u201310","journal-title":"IEEE Design & Test of Computers"},{"key":"5929_CR77","unstructured":"Xilinx (2020) http:\/\/www.xilinx.com"},{"key":"5929_CR78","unstructured":"Xilinx, Xst synthesis (2020) https:\/\/www.xilinx.com\/products\/design-tools\/xst.html"},{"key":"5929_CR79","doi-asserted-by":"crossref","unstructured":"Yang HH, and Wong D (2033) \u201cEfficient network flow based min-cut balanced partitioning,\u201d in The Best of ICCAD. Springer, pp. 521\u2013534","DOI":"10.1007\/978-1-4615-0292-0_41"},{"key":"5929_CR80","unstructured":"Yang S (1991) Logic synthesis and optimization benchmarks user guide, version 3.0"},{"key":"5929_CR81","doi-asserted-by":"crossref","unstructured":"Yarack E, and Carletta J (2000) \u201cAn evaluation of move-based multi-way partitioning algorithms,\u201d in Proceedings 2000 International Conference on Computer Design. IEEE, pp. 363\u2013369","DOI":"10.1109\/ICCD.2000.878309"},{"key":"5929_CR82","unstructured":"Zebu-server asic emulator by synopsys (2020) http:\/\/www.synopsys.com\/tools\/verification\/hardware-verification\/emulation\/Pages\/default.aspx"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05929-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-021-05929-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05929-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,11]],"date-time":"2021-06-11T06:41:52Z","timestamp":1623393712000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-021-05929-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2]]},"references-count":82,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2021,2]]}},"alternative-id":["5929"],"URL":"https:\/\/doi.org\/10.1007\/s10836-021-05929-1","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,2]]},"assertion":[{"value":"13 June 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 January 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 February 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}