{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:39:34Z","timestamp":1740123574567,"version":"3.37.3"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1007\/s10836-021-05939-z","type":"journal-article","created":{"date-parts":[[2021,4,15]],"date-time":"2021-04-15T05:59:01Z","timestamp":1618466341000},"page":"191-203","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs"],"prefix":"10.1007","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6840-9935","authenticated-orcid":false,"given":"Vasileios","family":"Gerakis","sequence":"first","affiliation":[]},{"given":"Yiorgos","family":"Tsiatouhas","sequence":"additional","affiliation":[]},{"given":"Alkis","family":"Hatzopoulos","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,4,14]]},"reference":[{"key":"5939_CR1","doi-asserted-by":"crossref","unstructured":"Fang X, Yu\u00a0Y, Peng X (2019)\u00a0\"TSV Prebond Test Method Based on Switched Capacitors,\" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(1):205\u2013218","DOI":"10.1109\/TVLSI.2018.2870482"},{"issue":"6","key":"5939_CR2","doi-asserted-by":"publisher","first-page":"1004","DOI":"10.1109\/TCAD.2016.2613928","volume":"36","author":"W Hsu","year":"2017","unstructured":"Hsu W, Kochte MA, Lee K (2017) Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. IEEE Trans Comput Aided Des Integr Circuits Syst 36(6):1004\u20131017","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"4","key":"5939_CR3","doi-asserted-by":"publisher","first-page":"699","DOI":"10.1109\/TCPMT.2017.2788896","volume":"8","author":"Y Huang","year":"2018","unstructured":"Huang Y, Pan C, Lin S, Guo M (2018) Machine-Learning Approach in Detection and Classification for Defects in TSV-Based 3-D IC. IEEE Transactions on Components, Packaging and Manufacturing Technology 8(4):699\u2013706","journal-title":"IEEE Transactions on Components, Packaging and Manufacturing Technology"},{"key":"5939_CR4","unstructured":"\"International Technology Roadmap for Semiconductors\" (2013)"},{"issue":"1","key":"5939_CR5","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1109\/TCAD.2018.2808453","volume":"38","author":"J Jang","year":"2019","unstructured":"Jang J, Cheong M, Kang S (2019) TSV Repair Architecture for Clustered Faults. IEEE Trans Comput Aided Des Integr Circuits Syst 38(1):190\u2013194","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"5939_CR6","doi-asserted-by":"crossref","unstructured":"Kannan S, Kim B, Ahn B (2012) \"Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects\". J Electron Test 28, 39\u201351","DOI":"10.1007\/s10836-011-5263-2"},{"issue":"1","key":"5939_CR7","doi-asserted-by":"publisher","first-page":"256","DOI":"10.1109\/TED.2009.2034508","volume":"57","author":"G Katti","year":"2010","unstructured":"Katti G, Stucchi M, De Meyer K, Dehaene W (2010) Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs. IEEE Trans Electron Devices 57(1):256\u2013262","journal-title":"IEEE Trans Electron Devices"},{"issue":"4","key":"5939_CR8","doi-asserted-by":"publisher","first-page":"697","DOI":"10.1109\/TCPMT.2013.2239362","volume":"4","author":"J Kim","year":"2014","unstructured":"Kim J, Cho J, Kim J, Yook J-M, Kim JC, Lee J, Park K, Pak JS (2014) High-Frequency Scalable Modeling and Analysis of a Differential Signal Through-Silicon Via. IEEE Transactions on Components, Packaging and Manufacturing Technology 4(4):697\u2013707","journal-title":"IEEE Transactions on Components, Packaging and Manufacturing Technology"},{"issue":"4","key":"5939_CR9","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3041026","volume":"13","author":"A Koneru","year":"2017","unstructured":"Koneru A, Kannan S, Chakrabarty K (2017) Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits. ACM Journal on Emerging Technologies in Computing Systems (JETC) 13(4):1\u201323","journal-title":"ACM Journal on Emerging Technologies in Computing Systems (JETC)"},{"key":"5939_CR10","doi-asserted-by":"crossref","unstructured":"Lee Y, Kim J, Choi\u00a0I, Kang S (2016)\u00a0\"A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs,\". Proc. International SoC Design Conference (ISOCC), Jeju, 129\u2013130","DOI":"10.1109\/ISOCC.2016.7799724"},{"issue":"10","key":"5939_CR11","doi-asserted-by":"publisher","first-page":"1759","DOI":"10.1109\/TCAD.2016.2611505","volume":"36","author":"Y Lee","year":"2017","unstructured":"Lee Y, Lim H, Kang S (2017) Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. IEEE Trans Comput Aided Des Integr Circuits Syst 36(10):1759\u20131763","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"5939_CR12","doi-asserted-by":"publisher","first-page":"27","DOI":"10.1007\/s10836-011-5261-4","volume":"28","author":"Y Lou","year":"2012","unstructured":"Lou Y, Yan Z, Zhang F et al (2012) Comparing Through-Silicon-Via (TSV) Void\/Pinhole Defect Self-Test Methods. J Electron Test 28:27\u201338","journal-title":"J Electron Test"},{"key":"5939_CR13","doi-asserted-by":"crossref","unstructured":"Maity DK, Roy\u00a0SK, Giri\u00a0C (2018) \"Identification of Faulty TSVs in 3D IC During Pre-Bond Testing,\". Proc. 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID), Pune, 109\u2013114","DOI":"10.1109\/VLSID.2018.46"},{"key":"5939_CR14","doi-asserted-by":"crossref","unstructured":"Maity D, Roy S, Giri\u00a0C, Rahaman  H (2018)\u00a0\"Identification of Faulty TSV with a Built-In Self-Test Mechanism,\". Proc. IEEE 27th Asian Test Symposium (ATS), Hefei,\u00a01\u20136","DOI":"10.1109\/ATS.2018.00012"},{"key":"5939_CR15","doi-asserted-by":"publisher","first-page":"741","DOI":"10.1007\/s10836-019-05824-w","volume":"35","author":"DK Maity","year":"2019","unstructured":"Maity DK, Roy SK, Giri C (2019) Identification of Random\/Clustered TSV Defects in 3D IC During Pre-Bond Testing. J Electron Test 35:741\u2013759","journal-title":"J Electron Test"},{"key":"5939_CR16","doi-asserted-by":"crossref","unstructured":"Metzler C, Todri A, Bosio A, Dilillo L, Girard\u00a0P, Virazel A (2012)\u00a0\"Through-Silicon-Via resistive-open defect analysis,\". Proc. 17th IEEE European Test Symposium (ETS), Annecy, 1\u20131","DOI":"10.1109\/ETS.2012.6233037"},{"key":"5939_CR17","doi-asserted-by":"publisher","first-page":"103","DOI":"10.1007\/s10836-011-5233-8","volume":"28","author":"B Noia","year":"2012","unstructured":"Noia B, Chakrabarty K, Marinissen EJ (2012) Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J Electron Test 28:103\u2013120","journal-title":"J Electron Test"},{"key":"5939_CR18","doi-asserted-by":"crossref","unstructured":"Papadopoulos S, Gerakis V, Tsiatouhas\u00a0Y, Hatzopoulos A (2017)\u00a0\"Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs,\". Proc. 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki ,\u00a01\u20136","DOI":"10.1109\/PATMOS.2017.8106985"},{"key":"5939_CR19","doi-asserted-by":"crossref","unstructured":"Rodr\u00edguez-Monta\u00f1\u00e9s R, Arum\u00ed\u00a0D, Figueras J (2019)\u00a0\"Postbond Test of Through-Silicon Vias With Resistive Open Defects,\" in IEEE Transact Very Large Scale Integrat (VLSI) Syst 27(11):2596\u20132607","DOI":"10.1109\/TVLSI.2019.2925971"},{"key":"5939_CR20","doi-asserted-by":"crossref","unstructured":"Sung H, Cho K, Yoon\u00a0K, Kang S (2017)\u00a0\"A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories,\" in IEEE Transact Very Large Scale Integrat (VLSI) Syst 22(11):2380\u20132387","DOI":"10.1109\/TVLSI.2013.2289964"},{"key":"5939_CR21","doi-asserted-by":"crossref","unstructured":"Ye\u00a0F, Chakrabarty K (2012)\u00a0\"TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation,\". Proc. DAC Design Auto Conference 2012, San Francisco, CA,\u00a01024\u20131030","DOI":"10.1145\/2228360.2228545"},{"key":"5939_CR22","doi-asserted-by":"crossref","unstructured":"You JW, Huang SY, Lin YH, Tsai MH, Kwai DM, Chou YF, Wu CW (2013) \"In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis,\" in IEEE Transact Very Large Scale Integrat (VLSI) Syst, 21:(3):443\u2013453.","DOI":"10.1109\/TVLSI.2012.2187543"},{"issue":"2","key":"5939_CR23","doi-asserted-by":"publisher","first-page":"506","DOI":"10.1109\/TCAD.2018.2887051","volume":"39","author":"Y Yu","year":"2020","unstructured":"Yu Y, Fang X, Peng X (2020) A Post-Bond TSV Test Method Based on RGC Parameters Measurement. IEEE Trans Comput Aided Des Integr Circuits Syst 39(2):506\u2013519","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"5939_CR24","doi-asserted-by":"publisher","first-page":"573","DOI":"10.1007\/s10836-017-5681-x","volume":"33","author":"B Zhang","year":"2017","unstructured":"Zhang B, Agrawal VD (2017) Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. J Electron Test 33:573\u2013589","journal-title":"J Electron Test"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05939-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-021-05939-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05939-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,7,28]],"date-time":"2021-07-28T05:07:23Z","timestamp":1627448843000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-021-05939-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":24,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2021,4]]}},"alternative-id":["5939"],"URL":"https:\/\/doi.org\/10.1007\/s10836-021-05939-z","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2021,4]]},"assertion":[{"value":"14 July 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 March 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 April 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}