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The CAT methodology consists of two stages. Stage\u00a01, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a <jats:italic>defect detection matrix<\/jats:italic> (DDM). In Stage\u00a02, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage\u00a01, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to\u00a0as  <jats:italic>full set<\/jats:italic>, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage\u00a01 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence\u2019s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects.<\/jats:p>","DOI":"10.1007\/s10836-021-05943-3","type":"journal-article","created":{"date-parts":[[2021,5,26]],"date-time":"2021-05-26T04:02:33Z","timestamp":1622001753000},"page":"161-189","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality"],"prefix":"10.1007","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6041-5599","authenticated-orcid":false,"given":"Zhan","family":"Gao","sequence":"first","affiliation":[]},{"given":"Min-Chun","family":"Hu","sequence":"additional","affiliation":[]},{"given":"Santosh","family":"Malagi","sequence":"additional","affiliation":[]},{"given":"Joe","family":"Swenton","sequence":"additional","affiliation":[]},{"given":"Jos","family":"Huisken","sequence":"additional","affiliation":[]},{"given":"Kees","family":"Goossens","sequence":"additional","affiliation":[]},{"given":"Erik Jan","family":"Marinissen","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,5,26]]},"reference":[{"key":"5943_CR1","doi-asserted-by":"crossref","unstructured":"Arum\u00ed D, Rodriguez-Montanes R, Figueras J (2008) Experimental Characterization of CMOS Interconnect Open Defects. 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