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Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle\u2019s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.<\/jats:p>","DOI":"10.1007\/s10836-021-05949-x","type":"journal-article","created":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T07:23:28Z","timestamp":1622532208000},"page":"383-394","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects"],"prefix":"10.1007","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7591-6484","authenticated-orcid":false,"given":"Thiago","family":"Copetti","sequence":"first","affiliation":[]},{"given":"Guilherme","family":"Cardoso Medeiros","sequence":"additional","affiliation":[]},{"given":"Mottaqiallah","family":"Taouil","sequence":"additional","affiliation":[]},{"given":"Said","family":"Hamdioui","sequence":"additional","affiliation":[]},{"given":"Let\u00edcia","family":"Bolzani Poehls","sequence":"additional","affiliation":[]},{"given":"Tiago","family":"Balen","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,6,1]]},"reference":[{"issue":"1","key":"5949_CR1","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1109\/TDMR.2015.2397032","volume":"15","author":"G Harutyunyan","year":"2015","unstructured":"Harutyunyan G, Tshagharyan G, Zorian Y (2015) Test and repair methodology for FinFET-based memories. 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