{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:05:30Z","timestamp":1767261930638,"version":"3.37.3"},"reference-count":36,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61974001"],"award-info":[{"award-number":["61974001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2021,8]]},"DOI":"10.1007\/s10836-021-05962-0","type":"journal-article","created":{"date-parts":[[2021,8,25]],"date-time":"2021-08-25T01:02:31Z","timestamp":1629853351000},"page":"489-502","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications"],"prefix":"10.1007","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0024-987X","authenticated-orcid":false,"given":"Aibin","family":"Yan","sequence":"first","affiliation":[]},{"given":"Aoran","family":"Cao","sequence":"additional","affiliation":[]},{"given":"Zhelong","family":"Xu","sequence":"additional","affiliation":[]},{"given":"Jie","family":"Cui","sequence":"additional","affiliation":[]},{"given":"Tianming","family":"Ni","sequence":"additional","affiliation":[]},{"given":"Patrick","family":"Girard","sequence":"additional","affiliation":[]},{"given":"Xiaoqing","family":"Wen","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,8,25]]},"reference":[{"issue":"6","key":"5962_CR1","doi-asserted-by":"publisher","first-page":"2874","DOI":"10.1109\/23.556880","volume":"43","author":"T Calin","year":"1996","unstructured":"Calin T, Nicolaidis M, Velazco R (1996) Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Trans Nucl Sci 43(6):2874\u20132878","journal-title":"IEEE Trans Nucl Sci"},{"key":"5962_CR2","first-page":"509","volume-title":"DONUT: A Double Node Upset Tolerant Latch","author":"N Eftaxiopoulos","year":"2015","unstructured":"Eftaxiopoulos N, Axelos N, Pekmestzi K (2015) DONUT: A Double Node Upset Tolerant Latch. Proc. IEEE Annual Symposium on VLSI, Montpellier, France, pp 509\u2013514"},{"key":"5962_CR3","first-page":"1","volume-title":"Delta DICE: A Double Node Upset Resilient Latch","author":"N Eftaxiopoulos","year":"2015","unstructured":"Eftaxiopoulos N, Axelos N, Zervakis G, Tsoumanis K, Pekmestzi K (2015) Delta DICE: A Double Node Upset Resilient Latch. Proc. IEEE International Midwest Symposium on Circuits and Systems, Fort Collins, USA, pp 1\u20134"},{"issue":"3","key":"5962_CR4","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1049\/iet-cdt.2008.0099","volume":"3","author":"M Fazeli","year":"2009","unstructured":"Fazeli M, Miremadi S, Ejlali A, Patooghy A (2009) Low Energy Single Event Upset\/Single Event Transient-Tolerant Latch for Deep Submicron Technologies. IET Comput Digital Tech 3(3):289\u2013303","journal-title":"IET Comput Digital Tech"},{"key":"5962_CR5","first-page":"1","volume-title":"A High Performance SEU Tolerant Latch for Nanoscale CMOS Technology","author":"Z Huang","year":"2014","unstructured":"Huang Z (2014) A High Performance SEU Tolerant Latch for Nanoscale CMOS Technology. Proc. IEEE Design Automation Test in Europe, Dresden, Germany, pp 1\u20135"},{"key":"5962_CR6","doi-asserted-by":"publisher","first-page":"349","DOI":"10.1007\/s10836-015-5533-5","volume":"31","author":"Z Huang","year":"2015","unstructured":"Huang Z, Liang H, Hellebrand S (2015) A High Performance SEU Tolerant Latch. Journal of Electronics Testing 31:349\u2013359","journal-title":"Journal of Electronics Testing"},{"issue":"4","key":"5962_CR7","doi-asserted-by":"publisher","first-page":"349","DOI":"10.1007\/s10836-015-5533-5","volume":"31","author":"Z Huang","year":"2015","unstructured":"Huang Z, Liang H, Hellebrand S (2015) A High Performance SNU Tolerant Latch. J Electron Test 31(4):349\u2013359","journal-title":"J Electron Test"},{"issue":"9","key":"5962_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1587\/elex.12.20150286","volume":"12","author":"X Hui","year":"2015","unstructured":"Hui X, Yun Z (2015) Circuit and Layout Combination Technique to Enhance Multiple Nodes Upset Tolerance in Latches. IEICE Electronics Express 12(9):1\u20137","journal-title":"IEICE Electronics Express"},{"issue":"9","key":"5962_CR9","doi-asserted-by":"publisher","first-page":"554","DOI":"10.1049\/el.2018.0558","volume":"54","author":"J Jiang","year":"2018","unstructured":"Jiang J, Xu Y, Ren J, Zhu W, Lin D, Xiao J, Kong W, Zou S (2018) Low-Cost Single Event Double-Upset Tolerant Latch Design. Electron Lett 54(9):554\u2013556","journal-title":"Electron Lett"},{"key":"5962_CR10","doi-asserted-by":"crossref","unstructured":"Katsarou K, Tsiatouhas Y (2014) Double Node Charge Sharing SEU Tolerant Latch Design,\u201d Proc. IEEE International Symposium on On-Line Testing and Robust System Design, Platja d'Aro, Spain, pp. 122\u2013127","DOI":"10.1109\/IOLTS.2014.6873683"},{"issue":"4","key":"5962_CR11","doi-asserted-by":"publisher","first-page":"330","DOI":"10.1049\/el.2014.4374","volume":"51","author":"K Katsarou","year":"2015","unstructured":"Katsarou K, Tsiatouhas Y (2015) Soft Error Interception Latch: Double Node Charge Sharing SNU Tolerant Design. Electron Lett 51(4):330\u2013332","journal-title":"Electron Lett"},{"key":"5962_CR12","doi-asserted-by":"crossref","unstructured":"Li Y, Wang H, Liu R, Chen L, Nofal I, Shi S, He A, Guo G, Baeg S, Wen S, Wong R, Chen M, Wu Q (2017)\u00a0A Quatro-Based 65 nm Flip-Flop Circuit for Soft-Error Resilience. IEEE Trans Nucl Sci 64(6):1554\u20131561","DOI":"10.1109\/TNS.2017.2704062"},{"issue":"6","key":"5962_CR13","doi-asserted-by":"publisher","first-page":"2934","DOI":"10.1109\/TNS.2016.2608911","volume":"63","author":"Y Li","year":"2016","unstructured":"Li Y, Wang H, Liu R, Chen L, Nofal I, Chen Q, He A, Guo G, Baeg S, Wen S, Wong R, Wu Q, Chen M (2016) A 65 nm Temporally Hardened Flip-Flop Circuit. IEEE Trans Nucl Sci 63(6):2934\u20132940","journal-title":"IEEE Trans Nucl Sci"},{"key":"5962_CR14","doi-asserted-by":"publisher","first-page":"537","DOI":"10.1007\/s10836-015-5551-3","volume":"31","author":"Y Li","year":"2015","unstructured":"Li Y, Wang H, Yao S, Yan X, Gao Z, Xu J (2015) Double Node Upsets Hardened Latch Circuits. Journal of Electronics Testing 31:537\u2013548","journal-title":"Journal of Electronics Testing"},{"key":"5962_CR15","doi-asserted-by":"publisher","first-page":"89","DOI":"10.1016\/j.microrel.2019.01.005","volume":"93","author":"H Li","year":"2019","unstructured":"Li H, Xiao L, Qi C (2019) High Robust and Cost Effective Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 93:89\u201397","journal-title":"Microelectron Reliab"},{"issue":"7","key":"5962_CR16","doi-asserted-by":"publisher","first-page":"1315","DOI":"10.1109\/TVLSI.2010.2047954","volume":"19","author":"S Lin","year":"2011","unstructured":"Lin S, Kim Y, Lombardi F (2011) Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS. IEEE Transactions on Very Large Scale Integration VLSI Systems 19(7):1315\u20131319","journal-title":"IEEE Transactions on Very Large Scale Integration VLSI Systems"},{"issue":"19","key":"5962_CR17","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1587\/elex.15.20180753","volume":"15","author":"D Lin","year":"2018","unstructured":"Lin D, Xu Y, Li X, Xie X, Jiang J, Ren J, Zhu H, Zhang Z, Zou S (2018) A Novel Self-Recoverable and Triple Nodes Upset Resilience DICE Latch. IEICE Electronics Express 15(19):1\u201310","journal-title":"IEICE Electronics Express"},{"key":"5962_CR18","first-page":"293","volume-title":"SEU and SET Modeling and Mitigation in Deep Submicron Technologies","author":"D Mavis","year":"2007","unstructured":"Mavis D, Eaton P (2007) SEU and SET Modeling and Mitigation in Deep Submicron Technologies. Proc. IEEE International Reliability Physics Symposium, Phoenix, USA, pp 293\u2013305"},{"key":"5962_CR19","doi-asserted-by":"crossref","unstructured":"Mitra S, Zhang M, Seifert N, Mak T, Kim\u00a0K (2007)\u00a0Built-in Soft Error Resilience for Robust System Design. Proc IEEE International Conference on IC Design and Technology, Austin, USA, pp. 1\u20136","DOI":"10.1109\/ICICDT.2007.4299587"},{"key":"5962_CR20","doi-asserted-by":"crossref","unstructured":"Namba K, Sakata M, Ito H (2010)\u00a0Single Event Induced Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Kyoto, Japan, pp. 280\u2013288","DOI":"10.1109\/DFT.2010.41"},{"issue":"7","key":"5962_CR21","doi-asserted-by":"publisher","first-page":"445","DOI":"10.1109\/TCSI.2011.2177135","volume":"59","author":"H Nan","year":"2012","unstructured":"Nan H, Choi K (2012) High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology. IEEE Trans Circuits Syst I Regul Pap 59(7):445\u20131457","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"5962_CR22","doi-asserted-by":"publisher","first-page":"1209","DOI":"10.1016\/j.microrel.2012.01.001","volume":"52","author":"H Nan","year":"2012","unstructured":"Nan H, Choi K (2012) Low Cost and Highly Reliable Hardened Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 52:1209\u20131214","journal-title":"Microelectron Reliab"},{"issue":"11","key":"5962_CR23","doi-asserted-by":"publisher","first-page":"1455","DOI":"10.1109\/TC.2010.24","volume":"59","author":"M Omana","year":"2010","unstructured":"Omana M, Rossi D, Metra C (2010) High-Performance Robust Latches. IEEE Trans Comput 59(11):1455\u20131465","journal-title":"IEEE Trans Comput"},{"issue":"3","key":"5962_CR24","doi-asserted-by":"publisher","first-page":"584","DOI":"10.1109\/TVLSI.2017.2772861","volume":"26","author":"C Peng","year":"2018","unstructured":"Peng C, Xiao S, Lu W, Zhang J, Wu X, Chen J, Lin Z (2018) Average 7T1R Nonvolatile SRAM With R\/W Margin Enhanced for Low-Power Application. IEEE Trans Very Large Scale Integr VLSI Syst 26(3):584\u2013588","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"key":"5962_CR25","doi-asserted-by":"publisher","first-page":"863","DOI":"10.1016\/j.microrel.2015.03.014","volume":"55","author":"C Qi","year":"2015","unstructured":"Qi C, Xiao L, Guo J (2015) Low Cost and Highly Reliable Radiation Hardened Latch Design in 65 nm CMOS Technology. Microelectron Reliab 55:863\u2013872","journal-title":"Microelectron Reliab"},{"key":"5962_CR26","doi-asserted-by":"publisher","first-page":"109","DOI":"10.1016\/j.microrel.2016.12.003","volume":"69","author":"R Ramin","year":"2017","unstructured":"Ramin R (2017) Single Event Double Node Upset Tolerance in MOS\/Spintronic Sequential and Combinational Logic Circuits. Microelectron Reliab 69:109\u2013114","journal-title":"Microelectron Reliab"},{"issue":"1","key":"5962_CR27","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1109\/TNS.2011.2178265","volume":"59","author":"X She","year":"2012","unstructured":"She X, Li N, Tong J (2012) SEU Tolerant Latch Based on Error Detection. IEEE Trans Nucl Sci 59(1):211\u2013214","journal-title":"IEEE Trans Nucl Sci"},{"key":"5962_CR28","doi-asserted-by":"crossref","unstructured":"Watkins A, Tragouodas S (2016)\u00a0A Highly Robust Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Storrs, USA, pp. 15\u201320","DOI":"10.1109\/DFT.2016.7684062"},{"key":"5962_CR29","first-page":"1","volume":"99","author":"A Watkins","year":"2017","unstructured":"Watkins A, Tragouodas S (2017) Radiation Hardened Latch Designs for Double and Triple Node Upsets. IEEE Trans Emerg Top Comput 99:1\u201310","journal-title":"IEEE Trans Emerg Top Comput"},{"issue":"6","key":"5962_CR30","doi-asserted-by":"publisher","first-page":"1978","DOI":"10.1109\/TVLSI.2017.2655079","volume":"25","author":"A Yan","year":"2017","unstructured":"Yan A, Huang Z, Yi M, Xu X, Ouyang Y, Liang H (2017) \u201cDouble-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. IEEE Trans Very Large Scale Integr VLSI Syst 25(6):1978\u20131982","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"key":"5962_CR31","first-page":"1","volume":"99","author":"A Yan","year":"2018","unstructured":"Yan A, Lai L, Zhang Y, Cui J, Huang Z, Song J, Guo J, Wen X (2018) Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS. IEEE Trans Emerg Top Comput 99:1\u201314","journal-title":"IEEE Trans Emerg Top Comput"},{"issue":"12","key":"5962_CR32","doi-asserted-by":"publisher","first-page":"1171","DOI":"10.1587\/transele.E98.C.1171","volume":"98","author":"A Yan","year":"2015","unstructured":"Yan A, Liang H, Huang Z, Jiang C, Yi M (2015) A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology. IEICE Trans Electron 98(12):1171\u20131178","journal-title":"IEICE Trans Electron"},{"key":"5962_CR33","doi-asserted-by":"crossref","unstructured":"Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. Proc IEEE Asian Test Symposium, pp. 43\u201348, Kolkata, India","DOI":"10.1109\/ATS47505.2019.000-2"},{"issue":"2","key":"5962_CR34","doi-asserted-by":"publisher","first-page":"407","DOI":"10.1109\/TVLSI.2018.2879341","volume":"27","author":"A Yan","year":"2019","unstructured":"Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Radiation-Hardened 14T SRAM Bitcell with Speed and Power Optimized for Space Application. IEEE Trans Very Large Scale Integr VLSI Syst 27(2):407\u2013415","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"issue":"2","key":"5962_CR35","doi-asserted-by":"publisher","first-page":"287","DOI":"10.1109\/TCSII.2018.2849028","volume":"66","author":"A Yan","year":"2019","unstructured":"Yan A, Yang K, Huang Z, Zhang J, Cui J, Fang X, Yi M, Wen X (2019) A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. IEEE Trans Circuits Syst II Express Briefs 66(2):287\u2013291","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"issue":"23","key":"5962_CR36","doi-asserted-by":"publisher","first-page":"1243","DOI":"10.1049\/el.2020.1823","volume":"56","author":"H Zhang","year":"2020","unstructured":"Zhang H, Liu Z, Jiang J, Xiao J, Zhang Z, Zou S (2020) High-Performance and Single Event Double-Upset-Immune Latch Design. Electron Lett 56(23):1243\u20131245","journal-title":"Electron Lett"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05962-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-021-05962-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05962-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,12]],"date-time":"2021-11-12T05:07:01Z","timestamp":1636693621000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-021-05962-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8]]},"references-count":36,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2021,8]]}},"alternative-id":["5962"],"URL":"https:\/\/doi.org\/10.1007\/s10836-021-05962-0","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2021,8]]},"assertion":[{"value":"3 February 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 July 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"25 August 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}