{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:20:39Z","timestamp":1755998439619,"version":"3.37.3"},"reference-count":48,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2021,8]]},"DOI":"10.1007\/s10836-021-05965-x","type":"journal-article","created":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T08:07:59Z","timestamp":1633939679000},"page":"515-532","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability"],"prefix":"10.1007","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3901-1746","authenticated-orcid":false,"given":"Hussein","family":"Bazzi","sequence":"first","affiliation":[]},{"given":"Hassen","family":"Aziza","sequence":"additional","affiliation":[]},{"given":"Mathieu","family":"Moreau","sequence":"additional","affiliation":[]},{"given":"Adnan","family":"Harb","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,10,11]]},"reference":[{"issue":"2","key":"5965_CR1","doi-asserted-by":"publisher","first-page":"179","DOI":"10.1016\/j.mejo.2013.10.013","volume":"45","author":"Z Abbas","year":"2014","unstructured":"Abbas Z et al (2014) Impact of Technology Scaling on Leakage Power in Nano-Scale Bulk CMOS Digital Standard Cells. Microelectron J 45(2):179\u2013195","journal-title":"Microelectron J"},{"key":"5965_CR2","doi-asserted-by":"crossref","unstructured":"Aziza H et al (2011) \"Evaluation of OxRAM cell variability impact on memory performances through electrical simulations.\" Non-Volatile Memory Technology Symposium Proceeding","DOI":"10.1109\/NVMTS.2011.6137089"},{"key":"5965_CR3","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1016\/j.microrel.2018.07.065","volume":"88","author":"H Aziza","year":"2018","unstructured":"Aziza H et al (2018) A lightweight write-assist scheme for reduced RRAM variability and power. Microelectron Reliab 88:6\u201310","journal-title":"Microelectron Reliab"},{"key":"5965_CR4","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1016\/j.sse.2018.02.005","volume":"142","author":"H Aziza","year":"2018","unstructured":"Aziza H et al (2018) Resistive RAMs as analog trimming elements. Solid-State Electron 142:52\u201355","journal-title":"Solid-State Electron"},{"key":"5965_CR5","doi-asserted-by":"crossref","unstructured":"Bai Y et al (2014) \"Study of Multi-Level Characteristics for 3D Vertical Resistive Switching Memory\". Sci Rep 4(1)","DOI":"10.1038\/srep05780"},{"key":"5965_CR6","doi-asserted-by":"crossref","unstructured":"Banerjee A (2018)\"Ultra-Low-Power Embedded SRAM Design for Battery-Operated and Energy-Harvested IoT Applications.\" Green Electronics","DOI":"10.5772\/intechopen.76765"},{"key":"5965_CR7","doi-asserted-by":"crossref","unstructured":"Bazzi H et al (2018) \"Design of Hybrid CMOS Non-Volatile SRAM Cells in 130nm RRAM Technology.\" 2018 30th International Conference on Microelectronics (ICM), Sousse, Tunisia 228\u2013231","DOI":"10.1109\/ICM.2018.8704119"},{"key":"5965_CR8","doi-asserted-by":"crossref","unstructured":"Bazzi H et al (2018) \"Novel RRAM CMOS Non-Volatile Memory Cells in 130nm Technology.\" ICCA, Beirut 390\u2013393","DOI":"10.1109\/COMAPP.2018.8460422"},{"key":"5965_CR9","doi-asserted-by":"crossref","unstructured":"Bazzi H et al (2020) \u201cNon-Volatile SRAM Memory Cells Based on ReRAM Technology.\u201d SN Applied Sciences. 2(9)","DOI":"10.1007\/s42452-020-03267-z"},{"key":"5965_CR10","doi-asserted-by":"crossref","unstructured":"Bazzi H et al (2020) \"RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications.\" Analog Integr Circ Sig Process","DOI":"10.1007\/s10470-020-01587-z"},{"key":"5965_CR11","doi-asserted-by":"crossref","unstructured":"Benoist A et al (2014) \"28nmadvancedCMOS resistive RAM solution as embedded non-volatile memory.\" In 2014 IEEE International Reliability Physics Symposium, pages 2E.6.1\u20132E.6.5","DOI":"10.1109\/IRPS.2014.6860604"},{"issue":"3","key":"5965_CR12","doi-asserted-by":"publisher","first-page":"674","DOI":"10.1109\/TED.2013.2296793","volume":"61","author":"M Bocquet","year":"2014","unstructured":"Bocquet M et al (2014) Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories. IEEE Trans Electron Devices 61(3):674\u2013681","journal-title":"IEEE Trans Electron Devices"},{"key":"5965_CR13","first-page":"1","volume":"2013","author":"M Bocquet","year":"2013","unstructured":"Bocquet M et al (2013) \u201cCompact modeling solutions for OxRAM memories.\u201d IEEE Faible Tension Faible Consommation. Paris 2013:1\u20134","journal-title":"Paris"},{"issue":"2","key":"5965_CR14","doi-asserted-by":"publisher","first-page":"146","DOI":"10.1109\/JETCAS.2016.2547718","volume":"6","author":"GW Burr","year":"2016","unstructured":"Burr GW et al (2016) Recent Progress in Phase-Change Memory Technology. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6(2):146\u2013162","journal-title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems"},{"key":"5965_CR15","doi-asserted-by":"crossref","unstructured":"Cabout T et al (2013) \"Temperature impact (up to 200oC) on performance and reliability of HfO2-based RRAMs.\" in Proc. IEEE International Memory Workshop V: 4\u20137","DOI":"10.1109\/IMW.2013.6582112"},{"key":"5965_CR16","doi-asserted-by":"crossref","unstructured":"Chang MF et al (2014) \"Challenges at Circuit Designs for Resistive-Type Nonvolatile Memory and Nonvolatile Logics in Mobile and Cloud Applications.\" 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)","DOI":"10.1109\/ICSICT.2014.7021430"},{"issue":"6","key":"5965_CR17","doi-asserted-by":"publisher","first-page":"1483","DOI":"10.1109\/JSSC.2012.2192661","volume":"47","author":"P Chiu","year":"2012","unstructured":"Chiu P et al (2012) Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications. IEEE J Solid-State Circuits 47(6):1483\u20131496","journal-title":"IEEE J Solid-State Circuits"},{"key":"5965_CR18","doi-asserted-by":"crossref","unstructured":"Diokh T et al (2013) \"Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO2-RRAM integrated in a 65nm CMOS technology.\" in Proc. IEEE International Reliability Physics Symposium 3\u20136","DOI":"10.1109\/IRPS.2013.6532043"},{"key":"5965_CR19","doi-asserted-by":"crossref","unstructured":"Dou C et al (2017) \"Challenges of Emerging Memory and Memristor Based Circuits: Nonvolatile Logics, IoT Security, Deep Learning and Neuromorphic Computing.\" 2017 IEEE 12th Int Conf ASIC (ASICON)","DOI":"10.1109\/ASICON.2017.8252431"},{"key":"5965_CR20","doi-asserted-by":"crossref","unstructured":"Fantini A et al (2013) \"Intrinsic switching variability in HfO2 RRAM.\" in Proc. IMW, Monterey, CA 30\u201333","DOI":"10.1109\/IMW.2013.6582090"},{"key":"5965_CR21","doi-asserted-by":"crossref","unstructured":"Gonzalez-Velo Y et al (2015) \"TID Impact on Process Modified CBRAM Cells.\" 2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Moscow 1\u20134","DOI":"10.1109\/RADECS.2015.7365685"},{"issue":"4","key":"5965_CR22","doi-asserted-by":"publisher","first-page":"143","DOI":"10.5121\/vlsic.2011.2412","volume":"2","author":"A Gurjar","year":"2011","unstructured":"Gurjar A et al (2011) An Analytical Approach to Design VLSI Implementation of Low Power, High Speed SRAM Cell Using Sub-micron Technology. International Journal of VLSI design & Communication Systems (VLSICS) 2(4):143\u2013153","journal-title":"International Journal of VLSI design & Communication Systems (VLSICS)"},{"key":"5965_CR23","doi-asserted-by":"crossref","unstructured":"Hajri B et al (2017) \"Oxide-based RRAM models for circuit designers: A comparative analysis.\" International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS). IEEE","DOI":"10.1109\/DTIS.2017.7930176"},{"key":"5965_CR24","doi-asserted-by":"publisher","first-page":"168963","DOI":"10.1109\/ACCESS.2019.2954753","volume":"7","author":"B Hajri","year":"2019","unstructured":"Hajri B et al (2019) RRAM Device Models: A Comparative Analysis With Experimental Validation. IEEE Access 7:168963\u2013168980","journal-title":"IEEE Access"},{"issue":"9","key":"5965_CR25","doi-asserted-by":"publisher","first-page":"2605","DOI":"10.1109\/TCSI.2014.2312499","volume":"61","author":"K Huang","year":"2014","unstructured":"Huang K et al (2014) A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element. IEEE Trans Circuits Syst I Regul Pap 61(9):2605\u20132613","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"5965_CR26","doi-asserted-by":"crossref","unstructured":"Ishibashi K, Osada K (2011) \"Low Power and Reliable SRAM Memory Cell and Array Design.\" Springer","DOI":"10.1007\/978-3-642-19568-6"},{"key":"5965_CR27","doi-asserted-by":"crossref","unstructured":"Joly Y et al (2010) \"Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications.\" International Conference on Solid-State and Integrated Circuit Technology","DOI":"10.1109\/ICSICT.2010.5667684"},{"key":"5965_CR28","doi-asserted-by":"crossref","unstructured":"Joly Y et al (2011) \"Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress.\" microelectronics reliability 51.9\u201311: 1561\u20131563","DOI":"10.1016\/j.microrel.2011.07.027"},{"key":"5965_CR29","doi-asserted-by":"crossref","unstructured":"Kang W et al (2016) \"Low Store Power, High Speed, High Density, Nonvolatile SRAM Design With Spin Hall Effect-Driven Magnetic Tunnel Junctions.\" IEEE Transactions on Nanotechnology 1\u20131","DOI":"10.1109\/TNANO.2016.2640338"},{"key":"5965_CR30","doi-asserted-by":"crossref","unstructured":"Kingra SK et al (2017) \"Stability Analysis of Hybrid CMOS-RRAM Based 4T-2R NVSRAM.\" 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)","DOI":"10.1109\/NEWCAS.2017.8010121"},{"key":"5965_CR31","doi-asserted-by":"crossref","unstructured":"Kobayashi M et al (2017) \"A Nonvolatile SRAM Integrated with Ferroelectric HfO2 Capacitor for Normally-off and Ultralow Power IoT Application.\" 2017 Symposium on VLSI Technology","DOI":"10.23919\/VLSIT.2017.7998161"},{"issue":"7","key":"5965_CR32","doi-asserted-by":"publisher","first-page":"3037","DOI":"10.1109\/TED.2017.2707664","volume":"64","author":"X Li","year":"2017","unstructured":"Li X et al (2017) Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore. IEEE Trans Electron Devices 64(7):3037\u20133040","journal-title":"IEEE Trans Electron Devices"},{"key":"5965_CR33","doi-asserted-by":"crossref","unstructured":"Majumdar S et al (2016) \"Hybrid CMOS-OxRAM based 4T-2R NVSRAM with efficient programming scheme.\" 2016 16twh Non-Volatile Memory Technology Symposium (NVMTS), Pittsburgh, PA 1-4","DOI":"10.1109\/NVMTS.2016.7781513"},{"key":"5965_CR34","unstructured":"Mazreah A et al (2008) \"A Low Power SRAM Base on Novel Word-Line Decoding.\" World Academy of Science"},{"key":"5965_CR35","doi-asserted-by":"publisher","first-page":"526","DOI":"10.1186\/1556-276X-9-526","volume":"9","author":"JS Meena","year":"2014","unstructured":"Meena JS et al (2014) Overview of emerging nonvolatile memory technologies. Nanoscale Res Lett 9:526","journal-title":"Nanoscale Res Lett"},{"issue":"9","key":"5965_CR36","doi-asserted-by":"publisher","first-page":"2461","DOI":"10.1109\/TED.2012.2202319","volume":"59","author":"F Nardi","year":"2012","unstructured":"Nardi F et al (2012) Resistive Switching by Voltage-Driven Ion Migration in Bipolar RRAM Part I\u202f: Experimental Study. IEEE Trans Electron Devices 59(9):2461\u20132467","journal-title":"IEEE Trans Electron Devices"},{"issue":"2","key":"5965_CR37","first-page":"173","volume":"12","author":"JM Portal","year":"2014","unstructured":"Portal JM et al (2014) An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies. Journal of Electronic Science and Technology 12(2):173\u2013181","journal-title":"Journal of Electronic Science and Technology"},{"issue":"4","key":"5965_CR38","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1109\/TNANO.2017.2703985","volume":"16","author":"J-M Portal","year":"2017","unstructured":"Portal J-M et al (2017) Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2)\/28 nm FDSOI CMOS Technology. IEEE Trans Nanotechnol 16(4):677\u2013686","journal-title":"IEEE Trans Nanotechnol"},{"key":"5965_CR39","doi-asserted-by":"publisher","first-page":"748","DOI":"10.1109\/JSSC.1987.1052809","volume":"22","author":"E Seevinck","year":"1987","unstructured":"Seevinck E, List FJ, Lohstroh J (1987) Static-Noise Margin Analysis of MOS SRAM cells. IEEE J Solid-State Circuits 22:748\u2013754","journal-title":"IEEE J Solid-State Circuits"},{"issue":"5","key":"5965_CR40","doi-asserted-by":"publisher","first-page":"667","DOI":"10.1109\/5.849164","volume":"88","author":"A Sheikholeslami","year":"2000","unstructured":"Sheikholeslami A, Gulak PG (2000) A survey of circuit innovation in ferroelectric random access memories. IEEE Proc 88(5):667\u2013689","journal-title":"IEEE Proc"},{"key":"5965_CR41","doi-asserted-by":"crossref","unstructured":"Sheu S et al (2013) \"A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application.\" 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore 245-248","DOI":"10.1109\/ASSCC.2013.6691028"},{"issue":"9","key":"5965_CR42","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TMAG.2019.2917655","volume":"55","author":"S Shreya","year":"2019","unstructured":"Shreya S et al (2019) Differential Spin Hall Effect-Based Nonvolatile Static Random Access Memory for Energy-Efficient and Fast Data Restoration Application. IEEE Trans Magn 55(9):1\u201311","journal-title":"IEEE Trans Magn"},{"key":"5965_CR43","doi-asserted-by":"publisher","first-page":"24","DOI":"10.3390\/jlpea7030024","volume":"7","author":"P Singh","year":"2017","unstructured":"Singh P et al (2017) Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read\/Write Ability for Internet of Things (IoT) Applications. J Low Power Electron Appl 7:24","journal-title":"J Low Power Electron Appl"},{"key":"5965_CR44","first-page":"101","volume":"2012","author":"O Turkyilmaz","year":"2012","unstructured":"Turkyilmaz O, \u201cRRAM-based FPGA for normally off, instantly on applications.\u201d, et al (2012) IEEE\/ACM International Symposium on Nanoscale Architectures. Amsterdam 2012:101\u2013108","journal-title":"Amsterdam"},{"issue":"5","key":"5965_CR45","doi-asserted-by":"publisher","first-page":"905","DOI":"10.1109\/TNANO.2014.2329915","volume":"13","author":"W Wei","year":"2014","unstructured":"Wei W et al (2014) Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation. IEEE Trans Nanotechnol 13(5):905\u2013916","journal-title":"IEEE Trans Nanotechnol"},{"key":"5965_CR46","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1109\/JEDS.2020.2972319","volume":"8","author":"W-X You","year":"2020","unstructured":"You W-X et al (2020) A New 8T Hybrid Nonvolatile SRAM with Ferroelectric FET. IEEE Journal of The Electron Devices Society 8:171\u2013175","journal-title":"IEEE Journal of The Electron Devices Society"},{"key":"5965_CR47","doi-asserted-by":"crossref","unstructured":"Zhang Y et al (2015) \"Read Performance: The Newest Barrier in Scaled STT-RAM.\" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(6):1170\u20131174","DOI":"10.1109\/TVLSI.2014.2326797"},{"key":"5965_CR48","unstructured":"http:\/\/literature.cdn.keysight.com\/litweb\/pdf\/B1500-90090.pdf"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05965-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-021-05965-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-021-05965-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,12]],"date-time":"2021-11-12T05:07:34Z","timestamp":1636693654000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-021-05965-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8]]},"references-count":48,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2021,8]]}},"alternative-id":["5965"],"URL":"https:\/\/doi.org\/10.1007\/s10836-021-05965-x","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2021,8]]},"assertion":[{"value":"20 April 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 August 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 October 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}