{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T11:06:31Z","timestamp":1762254391364,"version":"3.37.3"},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/100007245","name":"Microelectronics Advanced Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007245","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004361","name":"Texas Instruments","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004361","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1007\/s10836-023-06047-w","type":"journal-article","created":{"date-parts":[[2023,2,21]],"date-time":"2023-02-21T19:54:29Z","timestamp":1677009269000},"page":"57-69","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing"],"prefix":"10.1007","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3959-1293","authenticated-orcid":false,"given":"Isaac","family":"Bruce","sequence":"first","affiliation":[]},{"given":"Praise O.","family":"Farayola","sequence":"additional","affiliation":[]},{"given":"Shravan K.","family":"Chaganti","sequence":"additional","affiliation":[]},{"given":"Abalhassan","family":"Sheikh","sequence":"additional","affiliation":[]},{"given":"Srivaths","family":"Ravi","sequence":"additional","affiliation":[]},{"given":"Degang","family":"Chen","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,2,21]]},"reference":[{"key":"6047_CR1","doi-asserted-by":"publisher","first-page":"133","DOI":"10.1109\/VTS.2002.1011124","volume-title":"Testing high-speed SoCs using low-speed ATEs","author":"M Nourani","year":"2002","unstructured":"Nourani M, Chin J (2002) Testing high-speed SoCs using low-speed ATEs. Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), Monterey, CA, USA, pp 133\u2013138. https:\/\/doi.org\/10.1109\/VTS.2002.1011124"},{"key":"6047_CR2","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/I2MTC.2018.8409877","volume-title":"Low-cost and accurate DAC linearity test with ultrafast segmented model identification of linearity errors and removal of measurement errors (uSMILE-ROME)","author":"SK Chaganti","year":"2018","unstructured":"Chaganti SK, Chen T, Zhuang Y, Chen D (2018) Low-cost and accurate DAC linearity test with ultrafast segmented model identification of linearity errors and removal of measurement errors (uSMILE-ROME). 2018 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Houston, TX, pp 1\u20136. https:\/\/doi.org\/10.1109\/I2MTC.2018.8409877"},{"key":"6047_CR3","doi-asserted-by":"publisher","first-page":"1474","DOI":"10.1109\/ISCAS.2016.7527536","volume-title":"Low-cost dithering generator for accurate ADC linearity test","author":"Y Duan","year":"2016","unstructured":"Duan Y, Chen T, Chen D (2016) Low-cost dithering generator for accurate ADC linearity test. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montr\u00e9al, QC, Canada, pp 1474\u20131477. https:\/\/doi.org\/10.1109\/ISCAS.2016.7527536"},{"key":"6047_CR4","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/VTS.2015.7116249","volume-title":"Ultrafast stimulus error removal algorithm for ADC linearity test","author":"T Chen","year":"2015","unstructured":"Chen T, Chen D (2015) Ultrafast stimulus error removal algorithm for ADC linearity test. 2015 IEEE 33rd VLSI Test Symposium (VTS), Napa, CA, USA, pp 1\u20135. https:\/\/doi.org\/10.1109\/VTS.2015.7116249"},{"issue":"6","key":"6047_CR5","doi-asserted-by":"publisher","first-page":"3516","DOI":"10.1109\/TIM.2019.2936716","volume":"69","author":"T Chen","year":"2020","unstructured":"Chen T et al (2020) A low-cost on-chip built-in self-test solution for adc linearity test. IEEE Trans Instrum Meas 69(6):3516\u20133526. https:\/\/doi.org\/10.1109\/TIM.2019.2936716","journal-title":"IEEE Trans Instrum Meas"},{"key":"6047_CR6","doi-asserted-by":"publisher","first-page":"235","DOI":"10.1109\/IOLTS.2005.38","volume-title":"Integrating BIST techniques for on-line SoC testing","author":"A Manzone","year":"2005","unstructured":"Manzone A, Bernardi P, Grosso M, Rebaudengo M, Sanchez E, Reorda MS (2005) Integrating BIST techniques for on-line SoC testing. 11th IEEE International On-Line Testing Symposium, French Riviera, France, pp 235\u2013240. https:\/\/doi.org\/10.1109\/IOLTS.2005.38"},{"issue":"4","key":"6047_CR7","doi-asserted-by":"publisher","first-page":"47","DOI":"10.9790\/3021-04454759","volume":"4","author":"VC Khoo","year":"2014","unstructured":"Khoo VC (2014) A case study on the effectiveness of multi-sites test handler to improve of production output. IOSR J Eng 4(4):47\u201359. https:\/\/doi.org\/10.9790\/3021-04454759","journal-title":"IOSR J Eng"},{"key":"6047_CR8","doi-asserted-by":"publisher","first-page":"360","DOI":"10.1109\/ATS.2003.1250837","volume-title":"Lowering cost of test: parallel test or low-cost ATE?","author":"J Rivoir","year":"2003","unstructured":"Rivoir J (2003) Lowering cost of test: parallel test or low-cost ATE? Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03, Xi\u2019an, China, pp 360\u2013363. https:\/\/doi.org\/10.1109\/ATS.2003.1250837"},{"key":"6047_CR9","unstructured":"reducing_test. Reducing IC test costs through multisite and concurrent testing. https:\/\/www.techdesignforums.com\/practice\/technique\/reduce-test-costs-multisite-concurrent-testing\/. Accessed 3 Oct 2020"},{"issue":"1","key":"6047_CR10","doi-asserted-by":"publisher","first-page":"486","DOI":"10.1109\/TR.2014.2336395","volume":"64","author":"H Kim","year":"2015","unstructured":"Kim H, Lee Y, Kang S (2015) A novel massively parallel testing method using multi-root for high reliability. IEEE Trans Reliab 64(1):486\u2013496. https:\/\/doi.org\/10.1109\/TR.2014.2336395","journal-title":"IEEE Trans Reliab"},{"issue":"2","key":"6047_CR11","doi-asserted-by":"publisher","first-page":"293","DOI":"10.4218\/etrij.14.0113.0469","volume":"36","author":"D Han","year":"2014","unstructured":"Han D, Lee Y, Kang S (2014) A new multi-site test for system-on-chip using multi-site star test architecture. ETRI J 36(2):293\u2013300. https:\/\/doi.org\/10.4218\/etrij.14.0113.0469","journal-title":"ETRI J"},{"key":"6047_CR12","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/ETS.2014.6847808","volume-title":"Site dependencies in a multisite testing environment","author":"T Lehner","year":"2014","unstructured":"Lehner T, Kuhr A, Wahl M, Bruck R (2014) Site dependencies in a multisite testing environment. 2014 19th IEEE European Test Symposium (ETS), Paderborn, Germany, pp 1\u20136. https:\/\/doi.org\/10.1109\/ETS.2014.6847808"},{"key":"6047_CR13","doi-asserted-by":"publisher","first-page":"7","DOI":"10.1109\/DELTA.2006.85","volume-title":"Test cost saving and challenges in the implementation of \/spl times\/6 and \/spl times\/8 parallel testing on freescale 16-bit HCS12 microcontroller product family","author":"LB Kian","year":"2006","unstructured":"Kian LB (2006) Test cost saving and challenges in the implementation of \/spl times\/6 and \/spl times\/8 parallel testing on freescale 16-bit HCS12 microcontroller product family. Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA\u201906), Kuala Lumpur, Malaysia, pp 7\u201382. https:\/\/doi.org\/10.1109\/DELTA.2006.85"},{"key":"6047_CR14","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/VTS.2018.8368661","volume-title":"Real-time monitoring of test fallout data to quickly identify tester and yield issues in a multi-site environment","author":"Q Khasawneh","year":"2018","unstructured":"Khasawneh Q, Dworak J, Gui P, Williams B, Elliott AC, Muthaiah A (2018) Real-time monitoring of test fallout data to quickly identify tester and yield issues in a multi-site environment. 2018 IEEE 36th VLSI Test Symposium (VTS), San Francisco, CA, pp 1\u20136. https:\/\/doi.org\/10.1109\/VTS.2018.8368661"},{"key":"6047_CR15","unstructured":"Says AI (2021) Coping with parallel test site-to-site variation. Semicond Eng. https:\/\/semiengineering.com\/coping-with-parallel-test-site-to-site-variation\/. Accessed 5 May 2022"},{"key":"6047_CR16","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/VTS48691.2020.9107616","volume-title":"Quantile \u2013 quantile fitting approach to detect site to site variations in massive multi-site testing","author":"PO Farayola","year":"2020","unstructured":"Farayola PO, Chaganti SK, Obaidi AO, Sheikh A, Ravi S, Chen D (2020) Quantile \u2013 quantile fitting approach to detect site to site variations in massive multi-site testing. 2020 IEEE 38th VLSI Test Symposium (VTS), pp 1\u20136. https:\/\/doi.org\/10.1109\/VTS48691.2020.9107616"},{"key":"6047_CR17","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TIM.2021.3051666","volume":"70","author":"PO Farayola","year":"2021","unstructured":"Farayola PO, Chaganti SK, Obaidi AO, Sheikh A, Ravi S, Chen D (2021) Detection of site to site variations from volume measurement data in multisite semiconductor testing. IEEE Trans Instrum Meas 70:1\u201312. https:\/\/doi.org\/10.1109\/TIM.2021.3051666","journal-title":"IEEE Trans Instrum Meas"},{"key":"6047_CR18","unstructured":"Wold S, Esbensen K, Geladi P. Principal component analysis. p 16"},{"key":"6047_CR19","unstructured":"Rosenberg D. 1 distances between probability measures. p 4"},{"key":"6047_CR20","unstructured":"Acharya J, Luo M. An algorithmic and information-theoretic toolbox for massive data. p 5"},{"key":"6047_CR21","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TEST.2016.7805844","volume-title":"What we know after twelve years developing and deploying test data analytics solutions","author":"KM Butler","year":"2016","unstructured":"Butler KM, Nahar A, Daasch WR (2016) What we know after twelve years developing and deploying test data analytics solutions. 2016 IEEE International Test Conference (ITC), pp 1\u20138. https:\/\/doi.org\/10.1109\/TEST.2016.7805844"},{"key":"6047_CR22","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-68692-9","volume-title":"Ordinal optimization: soft optimization for hard problems","author":"Y-C Ho","year":"2007","unstructured":"Ho Y-C, Zhao Q-C, Jia Q-S (2007) Ordinal optimization: soft optimization for hard problems. Springer, New York"},{"key":"6047_CR23","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/DTIS53253.2021.9505144","volume-title":"Massive multisite variability-aware die distribution estimation for analog\/mixed-signal circuits test validation","author":"PO Farayola","year":"2021","unstructured":"Farayola PO, Bruce I, Chaganti SK, Sheikh A, Ravi S, Chen D (2021) Massive multisite variability-aware die distribution estimation for analog\/mixed-signal circuits test validation. 2021 16th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS), pp 1\u20136. https:\/\/doi.org\/10.1109\/DTIS53253.2021.9505144"},{"key":"6047_CR24","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/ETS50041.2021.9465402","volume-title":"An ordinal optimization-based approach to die distribution estimation for massive multi-site testing validation: a case study","author":"I Bruce","year":"2021","unstructured":"Bruce I et al (2021) An ordinal optimization-based approach to die distribution estimation for massive multi-site testing validation: a case study. 2021 IEEE European Test Symposium (ETS), pp 1\u20134. https:\/\/doi.org\/10.1109\/ETS50041.2021.9465402"},{"issue":"1","key":"6047_CR25","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1348\/000711005X48266","volume":"59","author":"D Steinley","year":"2006","unstructured":"Steinley D (2006) K-means clustering: a half-century synthesis. Br J Math Stat Psychol 59(1):1\u201334. https:\/\/doi.org\/10.1348\/000711005X48266","journal-title":"Br J Math Stat Psychol"},{"issue":"260","key":"6047_CR26","doi-asserted-by":"publisher","first-page":"583","DOI":"10.1080\/01621459.1952.10483441","volume":"47","author":"William H Kruskal","year":"1952","unstructured":"Kruskal William H, Allen Wallis W (1952) Use of ranks in one-criterion variance analysis. J Am Stat Assoc 47(260):583\u2013621. https:\/\/doi.org\/10.1080\/01621459.1952.10483441","journal-title":"J Am Stat Assoc"},{"key":"6047_CR27","unstructured":"Mood AM (1920) Introduction to the theory of statistics, 3rd edn. http:\/\/archive.org\/details\/in.ernet.dli.2015.132521. Accessed 21 Feb 2021"},{"key":"6047_CR28","doi-asserted-by":"publisher","first-page":"304","DOI":"10.1109\/ITC50571.2021.00042","volume-title":"Systematic hardware error identification and calibration for massive multisite testing","author":"PO Farayola","year":"2021","unstructured":"Farayola PO et al (2021) Systematic hardware error identification and calibration for massive multisite testing. IEEE International Test Conference (ITC), Anaheim, CA, USA, pp 304\u2013308. https:\/\/doi.org\/10.1109\/ITC50571.2021.00042"},{"key":"6047_CR29","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/VTS52500.2021.9794216","volume-title":"The least-squares approach to systematic error identification and calibration in semiconductor multisite testing","author":"PO Farayola","year":"2022","unstructured":"Farayola PO, Bruce I, Chaganti SK, Sheikh A, Ravi S, Chen D (2022) The least-squares approach to systematic error identification and calibration in semiconductor multisite testing. 2022 IEEE 40th VLSI Test Symposium (VTS), San Diego, CA, USA, pp 1\u20137. https:\/\/doi.org\/10.1109\/VTS52500.2021.9794216"},{"key":"6047_CR30","doi-asserted-by":"publisher","first-page":"189","DOI":"10.1109\/TEST.2000.894206","volume-title":"Variance reduction using wafer patterns in I\/sub ddQ\/ data","author":"WR Daasch","year":"2000","unstructured":"Daasch WR, McNames J, Bockelman D, Cota K (2000) Variance reduction using wafer patterns in I\/sub ddQ\/ data. Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), Atlantic City, NJ, USA, pp 189\u2013198. https:\/\/doi.org\/10.1109\/TEST.2000.894206"},{"issue":"5","key":"6047_CR31","doi-asserted-by":"publisher","first-page":"74","DOI":"10.1109\/MDT.2002.1033795","volume":"19","author":"WR Daasch","year":"2002","unstructured":"Daasch WR, McNames J, Madge R, Cota K (2002) Neighborhood selection for I\/sub DDQ\/ outlier screening at wafer sort. IEEE Des Test Comput 19(5):74\u201381. https:\/\/doi.org\/10.1109\/MDT.2002.1033795","journal-title":"IEEE Des Test Comput"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-023-06047-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-023-06047-w\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-023-06047-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,26]],"date-time":"2023-04-26T04:05:37Z","timestamp":1682481937000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-023-06047-w"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":31,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2023,2]]}},"alternative-id":["6047"],"URL":"https:\/\/doi.org\/10.1007\/s10836-023-06047-w","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2023,2]]},"assertion":[{"value":"21 December 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 January 2023","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 February 2023","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"I certify no actual or potential conflict of interest in this article.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of Interest"}},{"value":"The authors declare that they have no known competing financial interests or personal relationships that could influence the work reported in this paper.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing Interests"}}]}}