{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T05:57:50Z","timestamp":1775887070759,"version":"3.50.1"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"crossref","award":["62274052"],"award-info":[{"award-number":["62274052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100004543","name":"China Scholarship Council","doi-asserted-by":"crossref","award":["202206505003"],"award-info":[{"award-number":["202206505003"]}],"id":[{"id":"10.13039\/501100004543","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.1007\/s10836-023-06057-8","type":"journal-article","created":{"date-parts":[[2023,4,25]],"date-time":"2023-04-25T06:02:35Z","timestamp":1682402555000},"page":"189-205","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Cost-Effective Path Delay Defect Testing Using Voltage\/Temperature Analysis Based on Pattern Permutation"],"prefix":"10.1007","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7082-4211","authenticated-orcid":false,"given":"Tai","family":"Song","sequence":"first","affiliation":[]},{"given":"Zhengfeng","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Xiaohui","family":"Guo","sequence":"additional","affiliation":[]},{"given":"Krstic","family":"Milos","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,4,25]]},"reference":[{"key":"6057_CR1","doi-asserted-by":"publisher","first-page":"164","DOI":"10.1109\/DATE.2005.277","volume":"1","author":"S Biswas","year":"2005","unstructured":"Biswas S, Li P, Blanton R, Pileggi L (2005) Specification test compaction for analog circuits and mems [accelerometer and opamp examples]. In Proc Des Automat Test Eur 1:164\u2013169","journal-title":"In Proc Des Automat Test Eur"},{"key":"6057_CR2","doi-asserted-by":"crossref","unstructured":"Chen M, Orailoglu A (2008) Test cost minimization through adaptive test development. In Proc. IEEE Int Conf Circuit Des 234-239","DOI":"10.1109\/ICCD.2008.4751867"},{"issue":"12","key":"6057_CR3","doi-asserted-by":"publisher","first-page":"10794","DOI":"10.1109\/TPEL.2017.2763750","volume":"33","author":"X Cheng","year":"2018","unstructured":"Cheng X, Song R, Xie G, Zhang Y, Zhang Z (2018) A new FPGA-based segmented delay-line DPWM with compensation for critical path delays. In IEEE Transactions on Power Electronics 33(12):10794\u201310802","journal-title":"In IEEE Transactions on Power Electronics"},{"key":"6057_CR4","doi-asserted-by":"crossref","unstructured":"Heo J, Kim T (2021) Reusable delay path synthesis for lightening asynchronous pipeline controller. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1437-1450","DOI":"10.1109\/TVLSI.2021.3073383"},{"key":"6057_CR5","doi-asserted-by":"crossref","unstructured":"Huang NC, Cheng CW, Wu KC (2022) Timing variability-aware analysis and optimization for variable-latency designs. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 1, pp. 81-94","DOI":"10.1109\/TVLSI.2021.3109824"},{"key":"6057_CR6","doi-asserted-by":"crossref","unstructured":"Huang L, Song T, Jiang T (2022) Linear regression combined KNN algorithm to identify latent defects for imbalance data of ICs. Microelectron J 105641, ISSN 0026-2692,.mejo.2022.105641","DOI":"10.1016\/j.mejo.2022.105641"},{"key":"6057_CR7","doi-asserted-by":"crossref","unstructured":"Javvaji PK, Tragoudas S (2019) On the sensitization probability of a critical path considering process variations and path correlations. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 5, pp. 1196-1205","DOI":"10.1109\/TVLSI.2019.2893844"},{"issue":"3","key":"6057_CR8","doi-asserted-by":"publisher","first-page":"417","DOI":"10.1109\/TNANO.2017.2664895","volume":"16","author":"A Karel","year":"2017","unstructured":"Karel A, Comte M, Galliere JM, Azais F, Renovell M (2017) Influence of body-biasing, supply voltage, and temperature on the detection of resistive short defects in FDSOI Technology. In IEEE Transactions on Nanotechnology 16(3):417\u2013430","journal-title":"In IEEE Transactions on Nanotechnology"},{"key":"6057_CR9","doi-asserted-by":"crossref","unstructured":"Larrabee T (1992) Test pattern generation using Boolean satisfiablity. IEEE Trans Comput-Aided Des Integr Circuits Syst 11(1):4-15","DOI":"10.1109\/43.108614"},{"issue":"12","key":"6057_CR10","doi-asserted-by":"publisher","first-page":"1923","DOI":"10.1109\/TCAD.2011.2163159","volume":"30","author":"J Ma","year":"2011","unstructured":"Ma J, Tehranipoor M (2011) Layout-aware critical path delay test under maximum power supply noise Effects. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30(12):1923\u20131934. https:\/\/doi.org\/10.1109\/TCAD.2011.2163159","journal-title":"In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"6057_CR11","doi-asserted-by":"crossref","unstructured":"Maxwell P (2011) Adaptive Testing: Dealing with Process Variability. In Proc. IEEE Design & Test of Computers, vol. 28, no. 6, pp. 41-49","DOI":"10.1109\/MDT.2011.118"},{"key":"6057_CR12","doi-asserted-by":"publisher","unstructured":"Miyake Y, Kato T, Kajihara S (2020) Path Delay Measurement with Correction for Temperature and Voltage Variations. In Proc.2020 IEEE International Test Conference in Asia (ITC-Asia), pp. 112-117. https:\/\/doi.org\/10.1109\/ITC-Asia51099.2020.00031","DOI":"10.1109\/ITC-Asia51099.2020.00031"},{"key":"6057_CR13","doi-asserted-by":"crossref","unstructured":"Milor L (1998) A tutorial introduction to research on analog and mixed-signal circuit testing. IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., vol. 45, no. 10, pp. 1389-1407","DOI":"10.1109\/82.728852"},{"key":"6057_CR14","doi-asserted-by":"crossref","unstructured":"Pomeranz I, Reddy SM (2008) Transition path delay faults: A new path delay fault model for small and large delay defects. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp. 98-10","DOI":"10.1109\/TVLSI.2007.909796"},{"key":"6057_CR15","unstructured":"Shi CJR, Tian M (1998) Automatic test generation of linear analog circuits under parameter variations. In Proc. IEEE\/ACM Des. Automat. Conf., pp. 501-506"},{"issue":"7","key":"6057_CR16","doi-asserted-by":"publisher","first-page":"1056","DOI":"10.1109\/TCAD.2014.2305835","volume":"33","author":"M Shintani","year":"2014","unstructured":"Shintani M, Uezono T, Takahashi T, Hatayama K, Aikyo T, Masu K, Sato T (2014) A variability-aware adaptive test flow for test quality improvement. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33(7):1056\u20131066","journal-title":"In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"6057_CR17","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105549","author":"T Song","year":"2022","unstructured":"Song T, Huang Z, Yan Y (2022) Machine learning classification algorithm for VLSI test cost reduction. Integration. https:\/\/doi.org\/10.1016\/j.mejo.2022.105549","journal-title":"Integration"},{"key":"6057_CR18","doi-asserted-by":"publisher","first-page":"147965","DOI":"10.1109\/ACCESS.2020.3016039","volume":"8","author":"T Song","year":"2020","unstructured":"Song T, Liang H, Ni T, Huang Z, Lu Y, Wan J, Yan A (2020) Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm. IEEE Access 8:147965\u2013147972","journal-title":"IEEE Access"},{"key":"6057_CR19","doi-asserted-by":"crossref","unstructured":"Song T, Liang H, Sun Y, Huang Z, Yi M, Fang X, Yan A (2019) Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory. VTS 1-6","DOI":"10.1109\/VTS.2019.8758628"},{"key":"6057_CR20","doi-asserted-by":"crossref","unstructured":"Stratigopoulos HGD, Drineas P, Slamani M, Makris Y (2007) Non-RF to RF test correlation using learning machines: A case study. In Proc. IEEE VLSI Test Symp., pp. 9-14","DOI":"10.1109\/VTS.2007.41"},{"key":"6057_CR21","doi-asserted-by":"publisher","unstructured":"Takahashi T, Uezono T, Shintani M, Masu K, Sato T (2009) On-die parameter extraction from path-delay measurements. In Proc. 2009 IEEE Asian Solid-State Circuits Conference, pp. 101-104. https:\/\/doi.org\/10.1109\/ASSCC.2009.5357189","DOI":"10.1109\/ASSCC.2009.5357189"},{"key":"6057_CR22","doi-asserted-by":"crossref","unstructured":"Yilmaz E, Ozev S (2008) Dynamic test scheduling for analog circuits for improved test quality. In Proc IEEE Int Conf Comput Des 227-233","DOI":"10.1109\/ICCD.2008.4751866"},{"key":"6057_CR23","doi-asserted-by":"crossref","unstructured":"Yilmaz E, Ozev S, Butler K (2010) Adaptive test flow for mixed-signal\/RF circuits using learned information from device under test. In Proc IEEE Int Test Conf 1-10","DOI":"10.1109\/TEST.2010.5699271"},{"key":"6057_CR24","doi-asserted-by":"crossref","unstructured":"Yuan X, Owczarczyk P, Drake AJ, Tiner MD, Hui DT (2015) Design considerations for reconfigurable delay circuit to emulate system critical paths. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2714-2718","DOI":"10.1109\/TVLSI.2014.2364785"},{"key":"6057_CR25","doi-asserted-by":"publisher","unstructured":"Zhang M, Li H, Li X (2011) Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 11, pp. 1969-1982. https:\/\/doi.org\/10.1109\/TVLSI.2010.2075945","DOI":"10.1109\/TVLSI.2010.2075945"},{"issue":"5","key":"6057_CR26","doi-asserted-by":"publisher","first-page":"749","DOI":"10.1109\/TCAD.2010.2043570","volume":"29","author":"V Zolotov","year":"2010","unstructured":"Zolotov V, Xiong J, Fatemi H, Visweswariah C (2010) Statistical path selection for at-speed test. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(5):749\u2013759","journal-title":"In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-023-06057-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-023-06057-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-023-06057-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,27]],"date-time":"2023-06-27T06:27:23Z","timestamp":1687847243000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-023-06057-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":26,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,4]]}},"alternative-id":["6057"],"URL":"https:\/\/doi.org\/10.1007\/s10836-023-06057-8","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,4]]},"assertion":[{"value":"14 August 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 February 2023","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"25 April 2023","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of Interest"}}]}}