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Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130\u00a0nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry\u2019s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.<\/jats:p>","DOI":"10.1007\/s10836-024-06108-8","type":"journal-article","created":{"date-parts":[[2024,3,23]],"date-time":"2024-03-23T02:01:30Z","timestamp":1711159290000},"page":"245-257","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["A DfT Strategy for Guaranteeing ReRAM\u2019s Quality after Manufacturing"],"prefix":"10.1007","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7591-6484","authenticated-orcid":false,"given":"T. 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