{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,15]],"date-time":"2025-12-15T14:18:45Z","timestamp":1765808325349,"version":"3.37.3"},"reference-count":187,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2024,4]]},"DOI":"10.1007\/s10836-024-06117-7","type":"journal-article","created":{"date-parts":[[2024,4,15]],"date-time":"2024-04-15T07:01:50Z","timestamp":1713164510000},"page":"139-158","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["A Survey and Recent Advances: Machine Intelligence in Electronic Testing"],"prefix":"10.1007","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-1602-2036","authenticated-orcid":false,"given":"Soham","family":"Roy","sequence":"first","affiliation":[]},{"given":"Spencer K.","family":"Millican","sequence":"additional","affiliation":[]},{"given":"Vishwani D.","family":"Agrawal","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,4,15]]},"reference":[{"key":"6117_CR1","doi-asserted-by":"crossref","unstructured":"Abdallah L, Stratigopoulos H, Kelma C, Mir S (2010) Sensors for built-in alternate RF test. In Proc. 15th IEEE European Test Symposium (ETS), pp. 49\u201354","DOI":"10.1109\/ETSYM.2010.5512783"},{"issue":"5","key":"6117_CR2","doi-asserted-by":"publisher","first-page":"920","DOI":"10.1109\/TCAD.2008.917578","volume":"27","author":"E Acar","year":"2008","unstructured":"Acar E, Ozev S (2008) Defect-oriented testing of RF circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 27(5):920\u2013931","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR3","unstructured":"Adams RD (2003) High performance memory testing. Frontiers in Electronic Testing Book Series, Springer"},{"key":"6117_CR4","unstructured":"Agrawal VD, Mercer MR (1985) Testability measures \u2013 what do they tell us? In Proc. International Test Conf., (Philadelphia, PA), pp. 391\u2013396"},{"key":"6117_CR5","doi-asserted-by":"crossref","unstructured":"Akbay SS, Torres JL, Rumer JM, Chatterjee A, Amtsfield J (2006) Alternate test of RF front ends with IP constraints: frequency domain test generation and validation. In Proc. IEEE International Test Conference, pp. 1\u201310","DOI":"10.1109\/TEST.2006.297706"},{"key":"6117_CR6","doi-asserted-by":"crossref","unstructured":"Ankerst M, Breunig MM, Kriegel HP, Sander J (1999) OPTICS: Ordering points to identify the clustering structure. In Proceedings of the 1999 ACM SIGMOD International Conference on Management of Data, SIGMOD \u201999, (New York, NY, USA), Association for Computing Machinery, p. 49-60","DOI":"10.1145\/304182.304187"},{"key":"6117_CR7","unstructured":"Baldi P (2012) Autoencoders, unsupervised learning, and deep architectures. In Guyon I, Dror G, Lemaire V, Taylor G and Silver D, editors, Proceedings of ICML Workshop on Unsupervised and Transfer Learning, volume\u00a027 of Proceedings of Machine Learning Research, (Bellevue, Washington, USA), PMLR, pp. 37\u201349"},{"issue":"6","key":"6117_CR8","doi-asserted-by":"publisher","first-page":"1513","DOI":"10.1109\/TVLSI.2020.2976734","volume":"28","author":"S Banerjee","year":"2020","unstructured":"Banerjee S, Chaudhuri A, Chakrabarty K (2020) Analysis of the impact of process variations and manufacturing defects on the performance of carbon-nanotube FETs. IEEE Trans Very Large Scale Integr VLSI Syst 28(6):1513\u20131526","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"issue":"6","key":"6117_CR9","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1109\/MDAT.2016.2590985","volume":"33","author":"MJ Barragan","year":"2016","unstructured":"Barragan MJ, Stratigopoulos H, Mir S, Le-Gall H, Bhargava N, Bal A (2016) Practical simulation flow for evaluating analog\/mixed-signal test techniques. IEEE Des Test 33(6):46\u201354","journal-title":"IEEE Des Test"},{"key":"6117_CR10","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-011-7009-3","volume-title":"In-circuit testing","author":"J Bateson","year":"1985","unstructured":"Bateson J (1985) In-circuit testing. Van Nostrand Reinhold Company, New York"},{"key":"6117_CR11","doi-asserted-by":"crossref","unstructured":"Becker B, Drechsler R, Eggersgluess S, Sauer M (2014) Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. In Proc. 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 1\u201310","DOI":"10.1109\/DTIS.2014.6850674"},{"issue":"5","key":"6117_CR12","doi-asserted-by":"publisher","first-page":"177","DOI":"10.1049\/ip-e.1981.0037","volume":"128","author":"RG Bennetts","year":"1981","unstructured":"Bennetts RG, Maunder CM, Robinson GD (1981) CAMELOT: A computer-aided measure for logic testability. IEE Proceedings E - Computers and Digital Techniques 128(5):177\u2013189","journal-title":"IEE Proceedings E - Computers and Digital Techniques"},{"issue":"6","key":"6117_CR13","doi-asserted-by":"publisher","first-page":"464","DOI":"10.1109\/MDT.2006.136","volume":"23","author":"S Bhattacharya","year":"2006","unstructured":"Bhattacharya S, Chatterjee A (2006) A DFT approach for testing embedded systems using DC sensors. IEEE Des Test Comput 23(6):464\u2013475","journal-title":"IEEE Des Test Comput"},{"key":"6117_CR14","volume-title":"Hardware security: A hands-on learning approach","author":"S Bhunia","year":"2018","unstructured":"Bhunia S, Tehranipoor M (2018) Hardware security: A hands-on learning approach, 1st edn. Morgan Kaufmann","edition":"1"},{"key":"6117_CR15","volume-title":"Pattern recognition and machine learning","author":"C Bishop","year":"2006","unstructured":"Bishop C (2006) Pattern recognition and machine learning. Springer Publishing Company, Incorporated"},{"key":"6117_CR16","unstructured":"Brglez F (1984) On testability analysis of combinational circuits. Proc International Symp Circuits and Systems 221\u2013225"},{"key":"6117_CR17","unstructured":"Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark circuits and a targeted translator in FORTRAN. Proceedings of the IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 677\u2013692"},{"key":"6117_CR18","volume-title":"Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits","author":"ML Bushnell","year":"2013","unstructured":"Bushnell ML, Agrawal VD (2013) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer Publishing Company, Incorporated"},{"key":"6117_CR19","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1023\/A:1008207423859","volume":"10","author":"ML Bushnell","year":"1997","unstructured":"Bushnell ML, Giraldi J (1997) A functional decomposition method for redundancy identification and test generation. J Electronic Testing 10:175\u2013195","journal-title":"J Electronic Testing"},{"key":"6117_CR20","unstructured":"Chakradhar ST (1991) Neural network models and optimization methods for digital testing. PhD thesis, Rutgers University, USA"},{"key":"6117_CR21","doi-asserted-by":"crossref","unstructured":"Chakradhar ST, Agrawal VD (1991) A transitive closure based algorithm for test generation. In Proceedings of the 28th ACM\/IEEE Design Automation Conference, DAC \u201991, pp. 353\u2013358","DOI":"10.1145\/127601.127693"},{"key":"6117_CR22","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3958-2","volume-title":"Neural models and algorithms for digital testing","author":"ST Chakradhar","year":"1991","unstructured":"Chakradhar ST, Agrawal VD, Bushnell ML (1991) Neural models and algorithms for digital testing. Springer"},{"issue":"7","key":"6117_CR23","doi-asserted-by":"publisher","first-page":"1015","DOI":"10.1109\/43.238038","volume":"12","author":"ST Chakradhar","year":"1993","unstructured":"Chakradhar ST, Agrawal VD, Rothweiler SG (1993) A transitive closure algorithm for test generation. IEEE Trans Comput Aided Des Integr Circuits Syst 12(7):1015\u20131028","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"4","key":"6117_CR24","doi-asserted-by":"publisher","first-page":"92","DOI":"10.1109\/MDAT.2020.2988657","volume":"37","author":"A Chaudhuri","year":"2020","unstructured":"Chaudhuri A, Banerjee S, Park H, Kim J, Murali G, Lee E, Kim D, Lim SK, Mukhopadhyay S, Chakrabarty K (2020) Advances in design and test of monolithic 3-D ICs. IEEE Des Test 37(4):92\u2013100","journal-title":"IEEE Des Test"},{"key":"6117_CR25","doi-asserted-by":"crossref","unstructured":"Chen HH, Ling DD (1997) Power supply noise analysis methodology for deep-submicron VLSI chip design. In Proceedings of the 34th Annual Design Automation Conference, p. 638-643","DOI":"10.1145\/266021.266307"},{"key":"6117_CR26","doi-asserted-by":"publisher","first-page":"118254","DOI":"10.1016\/j.eswa.2022.118254","volume":"209","author":"S Chen","year":"2022","unstructured":"Chen S, Zhang Y, Hou X, Shang Y, Yang P (2022) Wafer map failure pattern recognition based on deep convolutional neural network. Expert Syst Appl 209:118254","journal-title":"Expert Syst Appl"},{"key":"6117_CR27","doi-asserted-by":"crossref","unstructured":"Cheng KT (1991) On removing redundancy in sequential circuits. In Proceedings of the 28th ACM\/IEEE Design Automation Conference (DAC), 1991, pp. 164\u2013169","DOI":"10.1145\/127601.127655"},{"key":"6117_CR28","volume-title":"Unified methods for VLSI simulation and test generation","author":"KT Cheng","year":"1989","unstructured":"Cheng KT, Agrawal VD (1989) Unified methods for VLSI simulation and test generation. Springer"},{"key":"6117_CR29","doi-asserted-by":"crossref","unstructured":"Cheng W, Tian Y, Reddy SM (2017) Volume diagnosis data mining. in Proc. 22nd IEEE European Test Symposium (ETS), pp. 1\u201310","DOI":"10.1109\/ETS.2017.7968238"},{"key":"6117_CR30","doi-asserted-by":"crossref","unstructured":"Chern M, Lee SW, Huang SY, Huang Y, Veda G, Tsai KHH, Cheng WT (2019) Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. In Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 341\u2013346","DOI":"10.1145\/3287624.3287692"},{"key":"6117_CR31","doi-asserted-by":"crossref","unstructured":"Cimino M, Lapuyade H, De Matos M, Taris T, Deval Y, Begueret JB (2006) A robust 130nm-CMOS built-in current sensor dedicated to RF applications. In Proc. Eleventh IEEE European Test Symposium (ETS\u201906), pp. 151\u2013158","DOI":"10.1109\/ETS.2006.6"},{"key":"6117_CR32","doi-asserted-by":"publisher","first-page":"44","DOI":"10.1109\/54.867894","volume":"17","author":"F Corno","year":"2000","unstructured":"Corno F, Reorda MS, Squillero G (2000) RT-level ITC\u201999 benchmarks and first ATPG results. IEEE Des Test Comput 17:44\u201353","journal-title":"IEEE Des Test Comput"},{"issue":"2","key":"6117_CR33","doi-asserted-by":"publisher","first-page":"215","DOI":"10.1111\/j.2517-6161.1958.tb00292.x","volume":"20","author":"DR Cox","year":"1958","unstructured":"Cox DR (1958) The regression analysis of binary sequences. J R Stat Soc B Methodol 20(2):215\u2013242","journal-title":"J R Stat Soc B Methodol"},{"key":"6117_CR34","unstructured":"Daasch WR, Madge R (2005) Data-driven models for statistical testing: measurements, estimates and residuals. In Proc. IEEE International Test Conference, pp. 10 pp.\u2013322"},{"issue":"3","key":"6117_CR35","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/MDT.1985.294737","volume":"2","author":"JR Day","year":"1985","unstructured":"Day JR (1985) A fault-driven, comprehensive redundancy algorithm. IEEE Des Test Comput 2(3):35\u201344","journal-title":"IEEE Des Test Comput"},{"key":"6117_CR36","volume-title":"Multivariate analysis: Methods and applications","author":"WR Dillon","year":"1984","unstructured":"Dillon WR, Goldstein M (1984) Multivariate analysis: Methods and applications. Wiley Publishing Company, Incorporated"},{"key":"6117_CR37","doi-asserted-by":"crossref","unstructured":"Ellouz S, Gamand P, Kelma C, Vandewiele B, Allard B, Combining internal probing with artificial neural networks for optimal RFIC testing. In Proc. IEEE International Test Conference, pp. 1\u20139","DOI":"10.1109\/TEST.2006.297705"},{"key":"6117_CR38","unstructured":"Evans RC (1981) Testing repairable RAMs and mostly good memories. In Proceedings International Test Conference, pp. 49\u201355"},{"key":"6117_CR39","doi-asserted-by":"crossref","unstructured":"Fagot C, Girard P, Landrault C (1997) On using machine learning for logic BIST. In Proc. IEEE International Test Conference, pp. 338\u2013346","DOI":"10.1109\/TEST.1997.639635"},{"issue":"9","key":"6117_CR40","doi-asserted-by":"publisher","first-page":"82","DOI":"10.1109\/MCOM.2003.1232241","volume":"41","author":"J Ferrario","year":"2003","unstructured":"Ferrario J, Wolf R, Moss S, Slamani M (2003) A low-cost test solution for wireless phone RFICs. IEEE Commun Mag 41(9):82\u201388","journal-title":"IEEE Commun Mag"},{"issue":"1","key":"6117_CR41","doi-asserted-by":"publisher","first-page":"119","DOI":"10.1006\/jcss.1997.1504","volume":"55","author":"Y Freund","year":"1997","unstructured":"Freund Y, Schapire RE (1997) A decision-theoretic generalization of on-line learning and an application to boosting. J Comput Syst Sci 55(1):119\u2013139","journal-title":"J Comput Syst Sci"},{"key":"6117_CR42","doi-asserted-by":"crossref","unstructured":"Fuchs WK, Chang MF (1989) Diagnosis and repair of large memories: a critical review and recent results, pp. 213\u2013225. Boston, MA: Springer US","DOI":"10.1007\/978-1-4615-6799-8_20"},{"issue":"12","key":"6117_CR43","doi-asserted-by":"publisher","first-page":"1137","DOI":"10.1109\/TC.1983.1676174","volume":"C\u201332","author":"H Fujiwara","year":"1983","unstructured":"Fujiwara H, Shimono T (1983) On the acceleration of test generation algorithms. IEEE Trans Comput C\u201332(12):1137\u20131144","journal-title":"IEEE Trans Comput"},{"key":"6117_CR44","volume-title":"Computers and intractability","author":"MR Garey","year":"1990","unstructured":"Garey MR, Johnson DS (1990) Computers and intractability. A guide to the theory of NP-completeness. W. H, Freeman and Co"},{"key":"6117_CR45","unstructured":"Gers FA, Schraudolph NN, Schmidhuber J (2003) Learning precise timing with LSTM recurrent networks. J Mach Learn Res 3(null)115-143"},{"key":"6117_CR46","doi-asserted-by":"crossref","unstructured":"Girard P, Nicolici N, Wen X, editors (2010) Power-aware testing and test strategies for low power devices. Springer","DOI":"10.1007\/978-1-4419-0928-2"},{"key":"6117_CR47","doi-asserted-by":"crossref","unstructured":"G\u00f3mez LR, Wunderlich H (2016) A neural-network-based fault classifier. In Proc. IEEE 25th Asian Test Symposium (ATS), pp. 144\u2013149","DOI":"10.1109\/ATS.2016.46"},{"issue":"3","key":"6117_CR48","doi-asserted-by":"publisher","first-page":"215","DOI":"10.1109\/TC.1981.1675757","volume":"C\u201330","author":"P Goel","year":"1981","unstructured":"Goel P (1981) An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Comput C\u201330(3):215\u2013222","journal-title":"IEEE Trans Comput"},{"key":"6117_CR49","doi-asserted-by":"crossref","unstructured":"Goldstein L (1979) Controllability\/observability analysis of digital circuits. IEEE Transactions on Circuits and Systems, vol.\u00a0CAS-26, no.\u00a09, pp. 685\u2013693, Sept. 1979","DOI":"10.1109\/TCS.1979.1084687"},{"issue":"5","key":"6117_CR50","doi-asserted-by":"publisher","first-page":"527","DOI":"10.1007\/s10836-014-5477-1","volume":"30","author":"LR G\u00f3mez","year":"2014","unstructured":"G\u00f3mez LR, Cook A, Indlekofer T, Hellebrand S, Wunderlich HJ (2014) Adaptive bayesian diagnosis of intermittent faults. J Electron Test 30(5):527\u2013540","journal-title":"J Electron Test"},{"issue":"12","key":"6117_CR51","doi-asserted-by":"publisher","first-page":"1091","DOI":"10.1016\/j.mejo.2005.04.064","volume":"36","author":"A Gopalan","year":"2005","unstructured":"Gopalan A, Margala M, Mukund PR (2005) A current based self-test methodology for RF front-end circuits. Microelectron J 36(12):1091\u20131102","journal-title":"Microelectron J"},{"issue":"1","key":"6117_CR52","doi-asserted-by":"publisher","first-page":"9","DOI":"10.1007\/s10836-013-5430-8","volume":"30","author":"U Guin","year":"2014","unstructured":"Guin U, DiMase D, Tehranipoor M (2014) Counterfeit integrated circuits: Detection, avoidance, and the challenges ahead. J Electron Test Theory Appl 30(1):9\u201323","journal-title":"J Electron Test Theory Appl"},{"key":"6117_CR53","unstructured":"Guyon I, Elisseeff A (2003) An introduction to variable and feature selection. J Mach Learn Res 3(null)1157-1182"},{"issue":"2","key":"6117_CR54","doi-asserted-by":"publisher","first-page":"154","DOI":"10.1109\/12.73586","volume":"40","author":"RW Haddad","year":"1991","unstructured":"Haddad RW, Dahbura AT, Sharma AB (1991) Increased throughput for the testing and repair of RAMs with redundancy. IEEE Trans Comput 40(2):154\u2013166","journal-title":"IEEE Trans Comput"},{"issue":"4","key":"6117_CR55","doi-asserted-by":"publisher","first-page":"499","DOI":"10.1109\/4.991388","volume":"37","author":"MM Hafed","year":"2002","unstructured":"Hafed MM, Abaskharoun N, Roberts GW (2002) A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits. IEEE J Solid-State Circuits 37(4):499\u2013514","journal-title":"IEEE J Solid-State Circuits"},{"issue":"1","key":"6117_CR56","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/82.913181","volume":"48","author":"RR Harrison","year":"2001","unstructured":"Harrison RR, Bragg JA, Hasler P, Minch BA, Deweerth SP (2001) A CMOS programmable analog memory-cell array using floating-gate circuits. IEEE Trans Circuits Syst II Analog Digit Signal Process 48(1):4\u201311","journal-title":"IEEE Trans Circuits Syst II Analog Digit Signal Process"},{"key":"6117_CR57","first-page":"100","volume":"28","author":"JA Hartigan","year":"1979","unstructured":"Hartigan JA, Wong MA (1979) Algorithm AS 136: A k-means clustering algorithm. J Roy Stat Soc 28:100\u2013108","journal-title":"J Roy Stat Soc"},{"key":"6117_CR58","doi-asserted-by":"crossref","unstructured":"Hasan N, Liu CL (1988) Minimum fault coverage in reconfigurable arrays. In Digest of Papers 18th International Symposium on Fault-Tolerant Computing, pp. 348\u2013353","DOI":"10.1109\/FTCS.1988.5342"},{"issue":"1","key":"6117_CR59","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TCSII.2001.913180","volume":"48","author":"P Hasler","year":"2001","unstructured":"Hasler P, Lande TS (2001) Overview of floating-gate devices, circuits, and systems. IEEE Trans Circuits Syst II Analog Digit Signal Process 48(1):1\u20133","journal-title":"IEEE Trans Circuits Syst II Analog Digit Signal Process"},{"issue":"7","key":"6117_CR60","doi-asserted-by":"publisher","first-page":"727","DOI":"10.1109\/T-C.1974.224021","volume":"C\u201323","author":"JP Hayes","year":"1974","unstructured":"Hayes JP, Friedman AD (1974) Test point placement to simplify fault detection. IEEE Trans Comput C\u201323(7):727\u2013735","journal-title":"IEEE Trans Comput"},{"key":"6117_CR61","volume-title":"Neural networks and learning machines","author":"SS Haykin","year":"2009","unstructured":"Haykin SS (2009) Neural networks and learning machines. Pearson Education, third edition, Upper Saddle River, NJ"},{"key":"6117_CR62","doi-asserted-by":"crossref","unstructured":"Hearst MA, Dumais ST, Osuna E, Platt J, Sch\u00f6lkopf B (1998) Support vector machines. 13:18\u201328","DOI":"10.1109\/5254.708428"},{"key":"6117_CR63","doi-asserted-by":"crossref","unstructured":"Henftling M, Wittmann H, Antreich KJ (1995) A formal non-heuristic ATPG approach. Proceedings of the Conference on European Design Automation, pp. 248\u2013253","DOI":"10.1109\/EURDAC.1995.527414"},{"key":"6117_CR64","unstructured":"Ho TK (1995) Random decision forests. in Proc International Conference on Document Analysis and Recognition (ICDAR), pp. 278\u2013282"},{"key":"6117_CR65","doi-asserted-by":"crossref","unstructured":"Ho TK (1995) Random decision forests. In Proceedings of 3rd International Conference on Document Analysis and Recognition, volume\u00a01, pp. 278\u2013282 vol. 1","DOI":"10.1109\/ICDAR.1995.598994"},{"issue":"6","key":"6117_CR66","doi-asserted-by":"publisher","first-page":"291","DOI":"10.1016\/0925-2312(92)90014-G","volume":"4","author":"M Hoehfeld","year":"1992","unstructured":"Hoehfeld M, Fahlman SE (1992) Probabilistic rounding in neural network learning with limited precision. Neurocomputing 4(6):291\u2013299","journal-title":"Neurocomputing"},{"key":"6117_CR67","doi-asserted-by":"crossref","unstructured":"Holler MA, Tam SM, Castro HA, Benson R (1989) An electrically trainable artificial neural network (ETANN) with 10240 \u2019floating gate\u2019 synapses. In Proc. International Joint Conference on Neural Networks, pp. 191\u2013196","DOI":"10.1109\/IJCNN.1989.118698"},{"key":"6117_CR68","doi-asserted-by":"publisher","first-page":"141","DOI":"10.1007\/BF00339943","volume":"52","author":"J Hopfield","year":"2004","unstructured":"Hopfield J, Tank D (2004) Neural computation of decisions in optimization problems. Biol Cybern 52:141\u2013152","journal-title":"Biol Cybern"},{"issue":"6","key":"6117_CR69","doi-asserted-by":"publisher","first-page":"417","DOI":"10.1037\/h0071325","volume":"24","author":"H Hotelling","year":"1933","unstructured":"Hotelling H (1933) Analysis of a complex of statistical variables into principal components. J Educ Psychol 24(6):417\u2013441","journal-title":"J Educ Psychol"},{"key":"6117_CR70","doi-asserted-by":"crossref","unstructured":"Huang Q, Fang C, Mittal S, Blanton RD (2018) Improving diagnosis efficiency via machine learning. In Proc. IEEE International Test Conference (ITC), pp. 1\u201310","DOI":"10.1109\/TEST.2018.8624884"},{"key":"6117_CR71","doi-asserted-by":"crossref","unstructured":"Huang Y, Benware B, Klingenberg R, Tang H, Dsouza J, Cheng WT (2017) Scan chain diagnosis based on unsupervised machine learning. In 2017 IEEE 26th Asian Test Symposium (ATS), pp. 225\u2013230","DOI":"10.1109\/ATS.2017.50"},{"issue":"3","key":"6117_CR72","doi-asserted-by":"publisher","first-page":"240","DOI":"10.1109\/MDT.2008.83","volume":"25","author":"Y Huang","year":"2008","unstructured":"Huang Y, Guo R, Cheng W, Li JC (2008) Survey of scan chain diagnosis. IEEE Design Test Comput 25(3):240\u2013248","journal-title":"IEEE Design Test Comput"},{"key":"6117_CR73","doi-asserted-by":"crossref","unstructured":"Huang Y, Hsieh H, Lu L (2007) A low-noise amplifier with integrated current and power sensors for RF BIST applications. In Proc. 25th IEEE VLSI Test Symposium (VTS\u201907), pp. 401\u2013408","DOI":"10.1109\/VTS.2007.7"},{"key":"6117_CR74","doi-asserted-by":"crossref","unstructured":"Huisman LM, Kassab M, Pastel L (2004) Data mining integrated circuit fails with fail commonalities. In Proc. International Test Conference, pp. 661\u2013668","DOI":"10.1109\/TEST.2004.1387327"},{"key":"6117_CR75","doi-asserted-by":"crossref","unstructured":"Immanuel J, Millican SK (2020) Calculating signal controllability using neural networks: improvements to testability analysis and test point insertion. In Proc. IEEE 29th North Atlantic Test Workshop (NATW), pp. 1\u20136","DOI":"10.1109\/NATW49237.2020.9153082"},{"issue":"4","key":"6117_CR76","doi-asserted-by":"publisher","first-page":"546","DOI":"10.1162\/neco.1991.3.4.546","volume":"3","author":"M Jabri","year":"1991","unstructured":"Jabri M, Flower B (1991) Weight perturbation: An optimal architecture and learning technique for analog VLSI feedforward and recurrent multilayer networks. Neural Comput 3(4):546\u2013565","journal-title":"Neural Comput"},{"key":"6117_CR77","doi-asserted-by":"publisher","first-page":"38","DOI":"10.1109\/MDT.1985.294683","volume":"2","author":"SK Jain","year":"1985","unstructured":"Jain SK, Agrawal VD (1985) Statistical fault analysis. IEEE Design Test Comput 2:38\u201344","journal-title":"IEEE Design Test Comput"},{"key":"6117_CR78","volume-title":"Burn-in","author":"F Jensen","year":"1982","unstructured":"Jensen F, Petersen NE (1982) Burn-in. John Wiley & Sons Inc, Chichester, UK"},{"key":"6117_CR79","doi-asserted-by":"crossref","unstructured":"Jiang YM, Cheng KT (1999) Analysis of performance impact caused by power supply noise in deep submicron devices. In Proceedings Design Automation Conference, pp. 760\u2013765","DOI":"10.1145\/309847.310053"},{"issue":"6","key":"6117_CR80","doi-asserted-by":"publisher","first-page":"985","DOI":"10.1109\/TCAD.2015.2481859","volume":"35","author":"S Jin","year":"2016","unstructured":"Jin S, Ye F, Zhang Z, Chakrabarty K, Gu X (2016) Efficient board-level functional fault diagnosis with missing syndromes. IEEE Trans Comput Aided Des Integr Circuits Syst 35(6):985\u2013998","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR81","unstructured":"Kaufman L, Rousseeuw PJ (2008) Partitioning around medoids (Program PAM), pp. 68\u2013125. John Wiley & Sons, Inc"},{"key":"6117_CR82","volume-title":"Advanced production testing of RF, SoC, and SiP devices","author":"J Kelly","year":"2007","unstructured":"Kelly J, Engelhardt M (2007) Advanced production testing of RF, SoC, and SiP devices. Artech House Inc, Boston"},{"key":"6117_CR83","unstructured":"Butler KM, Carulli Jr JM, Saxena J, Vasavada AP (2011) System and method for estimating test escapes in integrated circuits. U.S. Patent 7865849B2"},{"key":"6117_CR84","doi-asserted-by":"crossref","unstructured":"Kirkland T, Mercer MR (1987) A topological search algorithm for ATPG. Proceedings of the 24th ACM\/IEEE Design Automation Conference, pp. 502\u2013508","DOI":"10.1145\/37888.37963"},{"issue":"9","key":"6117_CR85","doi-asserted-by":"publisher","first-page":"1464","DOI":"10.1109\/5.58325","volume":"78","author":"T Kohonen","year":"2002","unstructured":"Kohonen T (2002) The self-organizing map. Proc IEEE 78(9):1464\u20131480","journal-title":"Proc IEEE"},{"issue":"5","key":"6117_CR86","doi-asserted-by":"publisher","first-page":"359","DOI":"10.1109\/TCSII.2002.802282","volume":"49","author":"VF Koosh","year":"2002","unstructured":"Koosh VF, Goodman RM (2002) Analog VLSI neural network with digital perturbative learning. IEEE Trans Circuits Syst II Analog\u00a0 Digit Signal Process 49(5):359\u2013368","journal-title":"IEEE Trans Circuits Syst II Analog\u00a0 Digit Signal Process"},{"key":"6117_CR87","volume-title":"Hierarchical test generation: Can AI help?","author":"B Krishnamurthy","year":"1987","unstructured":"Krishnamurthy B (1987) Hierarchical test generation: Can AI help? In Proc, International Test Conf"},{"key":"6117_CR88","doi-asserted-by":"crossref","unstructured":"Kunz W, Pradhan DK (1992) Recursive learning: An attractive alternative to the decision tree for test generation in digital circuits. In Proceedings of the IEEE International Test Conference, pp. 816\u2013825","DOI":"10.1109\/TEST.1992.527905"},{"issue":"1","key":"6117_CR89","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/MDT.1987.295111","volume":"4","author":"S Kuo","year":"1987","unstructured":"Kuo S, Fuchs WK (1987) Efficient spare allocation for reconfigurable arrays. IEEE Des Test Comput 4(1):24\u201331","journal-title":"IEEE Des Test Comput"},{"key":"6117_CR90","doi-asserted-by":"publisher","first-page":"1480","DOI":"10.1109\/ICNN.1996.549118","volume":"3","author":"J Laaksonen","year":"1996","unstructured":"Laaksonen J, Oja E (1996) Classification with learning k-nearest neighbors. In Proc. International Conference on Neural Networks (ICNN) 3:1480\u20131483","journal-title":"International Conference on Neural Networks (ICNN)"},{"key":"6117_CR91","doi-asserted-by":"crossref","unstructured":"Larrabee T (1989) Efficient generation of test patterns using Boolean difference. In Proceedings International Test Conference, pp. 795\u2013801","DOI":"10.1109\/TEST.1989.82368"},{"issue":"1","key":"6117_CR92","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/43.108614","volume":"11","author":"T Larrabee","year":"1992","unstructured":"Larrabee T (1992) Test pattern generation using boolean satisfiability. IEEE Trans CAD 11(1):4\u201315","journal-title":"IEEE Trans CAD"},{"issue":"1","key":"6117_CR93","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1109\/TCAD.2013.2282281","volume":"33","author":"YH Li","year":"2014","unstructured":"Li YH, Lien WC, Lin IC, Lee KJ (2014) Capture-power-safe test pattern determination for at-speed scan-based testing. IEEE Trans Comput Aided Des Integr Circuits Syst 33(1):127\u2013138","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR94","doi-asserted-by":"crossref","unstructured":"Li Z, Colburn JE, Pagalone V, Narayanun K, Chakrabarty K (2017) Test-cost optimization in a scan-compression architecture using support-vector regression. In Proc. IEEE 35th VLSI Test Symposium (VTS), pp. 1\u20136","DOI":"10.1109\/VTS.2017.7928956"},{"issue":"5","key":"6117_CR95","doi-asserted-by":"publisher","first-page":"1207","DOI":"10.1109\/TNN.2003.816370","volume":"14","author":"B Linares-Barranco","year":"2003","unstructured":"Linares-Barranco B, Serrano-Gotarredona T, Serrano-Gotarredona R (2003) Compact low-power calibration mini-DACs for neural arrays with programmable weights. IEEE Trans Neural Netw 14(5):1207\u20131216","journal-title":"IEEE Trans Neural Netw"},{"key":"6117_CR96","doi-asserted-by":"crossref","unstructured":"Littlestone N, Warmuth MK (1989) The weighted majority algorithm. In Proc. 30th Annual Symposium on Foundations of Computer Science, pp. 256\u2013261","DOI":"10.1109\/SFCS.1989.63487"},{"issue":"2","key":"6117_CR97","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1049\/iet-cdt.2016.0032","volume":"11","author":"Y Liu","year":"2017","unstructured":"Liu Y, Han C, Lin S, Li JC (2017) PSN-aware circuit test timing prediction using machine learning. IET Comput Digit Tech 11(2):60\u201367","journal-title":"IET Comput Digit Tech"},{"key":"6117_CR98","doi-asserted-by":"crossref","unstructured":"Lombardi F, Huang WK (1988) Approaches for the repair of VLSI\/WSI RRAMs by row\/column deletion. In Digest of Papers, 18th International Symposium on Fault-Tolerant Computing, pp. 342\u2013347","DOI":"10.1109\/FTCS.1988.5341"},{"issue":"3","key":"6117_CR99","doi-asserted-by":"publisher","first-page":"457","DOI":"10.1109\/72.129418","volume":"3","author":"JB Lont","year":"1992","unstructured":"Lont JB, Guggenbuhl W (1992) Analog CMOS implementation of a multilayer perceptron with nonlinear synapses. IEEE Trans Neural Netw 3(3):457\u2013465","journal-title":"IEEE Trans Neural Netw"},{"key":"6117_CR100","doi-asserted-by":"crossref","unstructured":"Ma Y, Ren H, Khailany B, Sikka H, Luo L, Natarajan K, Yu B (2019) High performance graph convolutional networks with applications in testability analysis. In Proc. 56th ACM\/IEEE Design Automation Conference (DAC), pp. 1\u20136","DOI":"10.1145\/3316781.3317838"},{"key":"6117_CR101","doi-asserted-by":"crossref","unstructured":"Maliuk D, Stratigopoulos HG, Huang H, Makris Y (2010) Analog neural network design for RF built-in self-test. In Proc. International Test Conference (ITC), pp. 23.2.1\u201323.2.10","DOI":"10.1109\/TEST.2010.5699272"},{"key":"6117_CR102","doi-asserted-by":"crossref","unstructured":"Manzini A, Inglese P, Caldi L, Cantero R, Carnevale G, Coppetta M, Giltrelli M, Mautone N, Irrera F, Ullmann R, Bernardi P (2019) A machine learning-based approach to optimize repair and increase yield of embedded flash memories in automotive systems-on-chip. In Proc. IEEE European Test Symposium (ETS), pp. 1\u20136","DOI":"10.1109\/ETS.2019.8791529"},{"key":"6117_CR103","doi-asserted-by":"crossref","unstructured":"Marques Silva JP, Sakallah KA (1996) GRASP - a new search algorithm for satisfiability. In Proceedings of International Conference on Computer Aided Design, pp. 220\u2013227","DOI":"10.1109\/ICCAD.1996.569607"},{"issue":"2","key":"6117_CR104","doi-asserted-by":"publisher","first-page":"151","DOI":"10.1016\/j.mejo.2006.08.003","volume":"38","author":"D Mateo","year":"2007","unstructured":"Mateo D, Altet J, Aldrete-Vidrio E (2007) Electrical characterization of analogue and RF integrated circuits by thermal measurements. Microelectron J 38(2):151\u2013156","journal-title":"Microelectron J"},{"issue":"1","key":"6117_CR105","doi-asserted-by":"publisher","first-page":"124","DOI":"10.1109\/43.184849","volume":"12","author":"P Mazumder","year":"1993","unstructured":"Mazumder P, Jih YS (1993) A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 12(1):124\u2013136","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"5","key":"6117_CR106","doi-asserted-by":"publisher","first-page":"1187","DOI":"10.1109\/TNN.2003.816369","volume":"14","author":"M Milev","year":"2003","unstructured":"Milev M, Hristov M (2003) Analog implementation of ANN with inherent quadratic nonlinearity of the synapses. IEEE Trans Neural Netw 14(5):1187\u20131200","journal-title":"IEEE Trans Neural Netw"},{"key":"6117_CR107","unstructured":"Millican S, Sun Y, Roy S, Agrawal V (2021) System and method for optimizing fault coverage based on optimized test point insertion determinations for logical circuits. U.S. Patent 17226950"},{"key":"6117_CR108","doi-asserted-by":"crossref","unstructured":"Millican SK, Sun Y, Roy S, Agrawal VD (2019) Applying neural networks to delay fault testing: test point insertion and random circuit training. In Proc. IEEE 28th Asian Test Symposium (ATS), pp. 13\u201318","DOI":"10.1109\/ATS47505.2019.000-7"},{"issue":"4","key":"6117_CR109","doi-asserted-by":"publisher","first-page":"395","DOI":"10.1007\/s10836-022-06020-z","volume":"38","author":"M Moness","year":"2022","unstructured":"Moness M, Gabor L, Hussein AI, Ali HM (2022) Automated design error debugging of digital VLSI circuits. J Electron Test Theory Appl 38(4):395\u2013417","journal-title":"J Electron Test Theory Appl"},{"issue":"2","key":"6117_CR110","doi-asserted-by":"publisher","first-page":"413","DOI":"10.1109\/72.557695","volume":"8","author":"AJ Montalvo","year":"1997","unstructured":"Montalvo AJ, Gyurcsik RS, Paulos JJ (1997) Toward a general-purpose analog VLSI neural network with on-chip learning. IEEE Trans Neural Netw 8(2):413\u2013423","journal-title":"IEEE Trans Neural Netw"},{"key":"6117_CR111","volume-title":"Introduction to linear regression analysis","author":"DC Montgomery","year":"2012","unstructured":"Montgomery DC, Peck EA, Vining GG (2012) Introduction to linear regression analysis. Wiley Publishing Company, Incorporated"},{"issue":"1","key":"6117_CR112","doi-asserted-by":"publisher","first-page":"27","DOI":"10.1007\/s10836-023-06044-z","volume":"39","author":"ZP Najafi-Haghi","year":"2023","unstructured":"Najafi-Haghi ZP, Wunderlich H (2023) Identifying resistive open defects in embedded cells under variations. J Electron Test Theory Appl 39(1):27\u201340","journal-title":"J Electron Test Theory Appl"},{"key":"6117_CR113","unstructured":"O\u2019Farrill C, Moakil-Chbany M, Eklow B (2005) Optimized reasoning-based diagnosis for non-random, board-level, production defects. in Proc. IEEE International Test Conference, pp. 1\u20137 (Paper 8.2)"},{"key":"6117_CR114","doi-asserted-by":"crossref","unstructured":"Ooi MP, Kwang Joo Sim E, Kuang YC, Kleeman L, Chan C, Demidenko S (2010) Automatic defect cluster extraction for semiconductor wafers. In Proc. IEEE Instrumentation Measurement Technology Conference Proceedings, pp. 1024\u20131029","DOI":"10.1109\/IMTC.2010.5488012"},{"key":"6117_CR115","unstructured":"Patel J, Patel S (1985) What heuristics are best for PODEM?. In Proc. First International Workshop on VLSI Design, pp. 1\u201320"},{"key":"6117_CR116","doi-asserted-by":"crossref","unstructured":"Patel S, Patel J (1986) Effectiveness of heuristics measures for automatic test pattern generation. In Proc. 23rd ACM\/IEEE Design Automation Conference (DAC), pp. 547\u2013552","DOI":"10.1109\/DAC.1986.1586141"},{"issue":"11","key":"6117_CR117","doi-asserted-by":"publisher","first-page":"559","DOI":"10.1080\/14786440109462720","volume":"2","author":"K Pearson","year":"1901","unstructured":"Pearson K (1901) On lines and planes of closest fit to systems of points in space. The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science 2(11):559\u2013572","journal-title":"The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science"},{"issue":"8","key":"6117_CR118","doi-asserted-by":"publisher","first-page":"1226","DOI":"10.1109\/TPAMI.2005.159","volume":"27","author":"H Peng","year":"2005","unstructured":"Peng H, Long F, Ding C (2005) Feature selection based on mutual information criteria of max-dependency, max-relevance, and min-redundancy. IEEE Trans Pattern Anal Mach Intell 27(8):1226\u20131238","journal-title":"IEEE Trans Pattern Anal Mach Intell"},{"key":"6117_CR119","doi-asserted-by":"crossref","unstructured":"Pradhan M, Bhattacharya BB (2020) A survey of digital circuit testing in the light of machine learning. WIREs Data Mining Knowl Discov 1\u201318","DOI":"10.1002\/widm.1360"},{"issue":"12","key":"6117_CR120","doi-asserted-by":"publisher","first-page":"2343","DOI":"10.1109\/TCAD.2018.2878169","volume":"38","author":"M Pradhan","year":"2019","unstructured":"Pradhan M, Bhattacharya BB, Chakrabarty K, Bhattacharya BB (2019) Predicting $${X}$$-sensitivity of circuit-inputs on test-coverage: A machine-learning approach. IEEE Trans Comput Aided Des Integr Circuits Syst 38(12):2343\u20132356","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"1","key":"6117_CR121","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/BF00116251","volume":"1","author":"JR Quinlan","year":"1986","unstructured":"Quinlan JR (1986) Induction of decision trees. Mach Learn 1(1):81\u2013106","journal-title":"Mach Learn"},{"issue":"2","key":"6117_CR122","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1049\/ip-e.1987.0019","volume":"134","author":"MW Roberts","year":"1987","unstructured":"Roberts MW, Lala PK (1987) Algorithm to detect reconvergent fanouts in logic circuits. IEE Proceedings E - Computers and Digital Techniques 134(2):105\u2013111","journal-title":"IEE Proceedings E - Computers and Digital Techniques"},{"issue":"5","key":"6117_CR123","doi-asserted-by":"publisher","first-page":"567","DOI":"10.1109\/PGEC.1967.264743","volume":"EC\u201316","author":"JP Roth","year":"1967","unstructured":"Roth JP, Bouricius WG, Schneider PR (1967) Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits. IEEE Transactions on Electronic Computers EC\u201316(5):567\u2013580","journal-title":"IEEE Transactions on Electronic Computers"},{"key":"6117_CR124","unstructured":"Roy S (2021) Toward zero backtracks in test pattern search algorithms with machine learning. PhD thesis, Auburn University, USA"},{"key":"6117_CR125","doi-asserted-by":"crossref","unstructured":"Roy S, Agrawal VD (2024) An amalgamated testability measure derived from machine intelligence. in Proceedings of 37th International Conference on VLSI Design & 23rd International Conference on Embedded Systems","DOI":"10.1109\/VLSID60093.2024.00123"},{"key":"6117_CR126","doi-asserted-by":"crossref","unstructured":"Roy S, Millican SK, Agrawal VD (2020) Machine intelligence for efficient test pattern generation. In Proceedings of the IEEE International Test Conference, (Washington D.C), pp. 1\u20135","DOI":"10.1109\/ITC44778.2020.9325250"},{"key":"6117_CR127","doi-asserted-by":"crossref","unstructured":"Roy S, Millican SK, Agrawal VD (2021) Principal component analysis in machine intelligence-based test generation. In Proc. IEEE Microelectronics Design and Test Symp. (MDTS\u201921), (USA), pp. 1\u20136","DOI":"10.1109\/MDTS52103.2021.9476085"},{"key":"6117_CR128","doi-asserted-by":"crossref","unstructured":"Roy S, Millican SK, Agrawal VD (2021) Special session - machine learning in test: A survey of analog, digital, memory, and RF integrated circuits. In Proc. IEEE VLSI Test Symp. (VTS\u201921), (USA), Apr. 2021, pp. 1\u201310","DOI":"10.1109\/VTS50974.2021.9441051"},{"key":"6117_CR129","doi-asserted-by":"crossref","unstructured":"Roy S, Millican SK, Agrawal VD (2021) Training neural network for machine intelligence in automatic test pattern generator. In Proceedings of 34th International Conference on VLSI Design & 20th International Conference on Embedded Systems, pp. 316\u2013321","DOI":"10.1109\/VLSID51830.2021.00059"},{"key":"6117_CR130","doi-asserted-by":"crossref","unstructured":"Roy S, Millican SK, Agrawal VD (2021) Unsupervised learning in test generation for digital integrated circuits. In Proceedings of the IEEE European Test Symposium, pp. 1\u20134","DOI":"10.1109\/ETS50041.2021.9465403"},{"key":"6117_CR131","doi-asserted-by":"crossref","unstructured":"Roy S, Millican SK, Agrawal VD (2022) Multi-heuristic machine intelligence guidance in automatic test pattern generation. In Proc. 31st Microelectronics Design and Test Symposium (MDTS), pp. 1\u20136","DOI":"10.1109\/MDTS54894.2022.9826985"},{"key":"6117_CR132","doi-asserted-by":"crossref","unstructured":"Roy S, Stiene B, Millican SK, Agrawal VD (2019) Improved random pattern delay fault coverage using inversion test points. In Proc. IEEE 28th North Atlantic Test Workshop (NATW), pp. 206\u2013211","DOI":"10.1109\/NATW.2019.8758727"},{"issue":"1","key":"6117_CR133","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1007\/s10836-020-05859-4","volume":"36","author":"S Roy","year":"2020","unstructured":"Roy S, Stiene B, Millican SK, Agrawal VD (2020) Improved pseudo-random fault coverage through inversions: A study on test point architectures. J Electron Testing Theory Applic 36(1):123\u2013133","journal-title":"J Electron Testing Theory Applic"},{"issue":"6","key":"6117_CR134","doi-asserted-by":"publisher","first-page":"571","DOI":"10.1007\/s10836-005-3735-y","volume":"21","author":"JY Ryu","year":"2005","unstructured":"Ryu JY, Kim BC (2005) Low-cost testing of 5 GHz low noise amplifiers using new RF BIST circuit. J Electron Test Theory Appl 21(6):571\u2013581","journal-title":"J Electron Test Theory Appl"},{"key":"6117_CR135","doi-asserted-by":"crossref","unstructured":"Savir (1983) Good controllability and observability do not guarantee good testability. IEEE Transactions on Computers C-32(12)","DOI":"10.1109\/TC.1983.1676183"},{"key":"6117_CR136","doi-asserted-by":"crossref","unstructured":"Sch\u00f6lkopf B, Smola AJ, editors (2001) Learning with kernels: support vector machines, regularization, optimization, and beyond. MIT Press","DOI":"10.7551\/mitpress\/4175.001.0001"},{"key":"6117_CR137","unstructured":"Schulz MH, Auth E (1988) Advanced automatic test pattern generation and redundancy identification techniques. In Digest of Papers, 18th International Symposium on Fault-Tolerant Computing, pp. 30\u201335"},{"issue":"7","key":"6117_CR138","doi-asserted-by":"publisher","first-page":"811","DOI":"10.1109\/43.31539","volume":"8","author":"MH Schulz","year":"1989","unstructured":"Schulz MH, Auth E (1989) Improved deterministic test pattern generation with applications to redundancy identification. IEEE Trans Comput Aided Des Integr Circuits Syst 8(7):811\u2013816","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"1","key":"6117_CR139","doi-asserted-by":"publisher","first-page":"126","DOI":"10.1109\/43.3140","volume":"7","author":"MH Schulz","year":"1988","unstructured":"Schulz MH, Trischler E, Sarfert TM (1988) SOCRATES: A highly efficient automatic test pattern generation system. IEEE Trans Comput Aided Des Integr Circuits Syst 7(1):126\u2013137","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR140","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1016\/0167-9260(89)90059-X","volume":"7","author":"SC Seth","year":"1989","unstructured":"Seth SC, Agrawal VD (1989) A new model for computation of probabilistic testability in combinational circuits. Integr VLSI J 7:49\u201375","journal-title":"Integr VLSI J"},{"issue":"4","key":"6117_CR141","doi-asserted-by":"publisher","first-page":"582","DOI":"10.1109\/12.54854","volume":"39","author":"SC Seth","year":"1990","unstructured":"Seth SC, Agrawal VD, Farhat H (1990) A statistical theory of digital circuit testability. IEEE Trans Comput 39(4):582\u2013586","journal-title":"IEEE Trans Comput"},{"key":"6117_CR142","doi-asserted-by":"crossref","unstructured":"Shan C, Babighian P, Pan Y, Carulli J, Wang L (2017) Systematic defect detection methodology for volume diagnosis: A data mining perspective. In Proc. IEEE International Test Conference (ITC), pp. 1\u201310","DOI":"10.1109\/TEST.2017.8242050"},{"key":"6117_CR143","unstructured":"Shepard KL, Narayanan V (1996) Noise in deep submicron digital design. In Proceedings of International Conference on Computer Aided Design, pp. 524\u2013531"},{"key":"6117_CR144","unstructured":"Silva E, Pineda de Gyvez J, Gronthoud G (2005) Functional vs. multi-VDD testing of RF circuits. In Proc. IEEE International Test Conference, pp. 9\u2013420"},{"key":"6117_CR145","doi-asserted-by":"publisher","first-page":"53","DOI":"10.1007\/s11047-004-3591-1","volume":"4","author":"A Singh","year":"2005","unstructured":"Singh A, Bharadwaj LM, Harpreet S (2005) DNA and quantum based algorithms for VLSI circuits testing. Nat Comput 4:53\u201372","journal-title":"Nat Comput"},{"key":"6117_CR146","doi-asserted-by":"crossref","unstructured":"Singh S, Singh A (2003) Applying quantum search to automated test pattern generation for VLSI circuits. In Proc. 4th International Conf. on Parallel and Distributed Computing, Applications and Technologies, (Chengdu, China), pp. 648\u2013651","DOI":"10.1109\/PDCAT.2003.1236383"},{"issue":"8","key":"6117_CR147","doi-asserted-by":"publisher","first-page":"1176","DOI":"10.1109\/TCAD.2009.2020721","volume":"28","author":"A Singhee","year":"2009","unstructured":"Singhee A, Rutenbar RA (2009) Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design. IEEE Trans Comput Aided Des Integr Circuits Syst 28(8):1176\u20131189","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR148","doi-asserted-by":"crossref","unstructured":"Skabar A (2003) Single-class classifier learning using neural networks: An application to the prediction of mineral deposits. In Proceedings of the 2003 International Conference on Machine Learning and Cybernetics, volume\u00a04, pp. 2127\u20132132 Vol.4","DOI":"10.1109\/ICMLC.2003.1259857"},{"issue":"3","key":"6117_CR149","doi-asserted-by":"publisher","first-page":"398","DOI":"10.1147\/rd.243.0398","volume":"24","author":"CH Stapper","year":"1980","unstructured":"Stapper CH, McLaren AN, Dreckmann M (1980) Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product. IBM J Res Dev 24(3):398\u2013409","journal-title":"IBM J Res Dev"},{"key":"6117_CR150","doi-asserted-by":"publisher","first-page":"1167","DOI":"10.1109\/43.536723","volume":"15","author":"P Stephan","year":"1996","unstructured":"Stephan P, Brayton RK, Sangiovanni-Vincentelli AL (1996) Combinational test generation using satisfiability. IEEE Trans Comput Aided Des Integr Circuits Syst 15:1167\u20131176","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR151","unstructured":"Stephenson JE, Grason J (1976) A testability measure for register transfer level digital circuits. In Proc. 6th International Fault Tolerant Computing Symp, pp. 101\u2013107"},{"key":"6117_CR152","doi-asserted-by":"crossref","unstructured":"Stratigopoulos H (2018) Machine learning applications in IC testing. In Proc. IEEE 23rd European Test Symposium (ETS), pp. 1\u201310","DOI":"10.1109\/ETS.2018.8400701"},{"issue":"2","key":"6117_CR153","doi-asserted-by":"publisher","first-page":"339","DOI":"10.1109\/TCAD.2007.907232","volume":"27","author":"H Stratigopoulos","year":"2008","unstructured":"Stratigopoulos H, Makris Y (2008) Error moderation in low-cost machine-learning-based analog\/RF testing. IEEE Trans Comput Aided Des Integr Circuits Syst 27(2):339\u2013351","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"4","key":"6117_CR154","doi-asserted-by":"publisher","first-page":"71","DOI":"10.1109\/MDT.2012.2205480","volume":"29","author":"H Stratigopoulos","year":"2012","unstructured":"Stratigopoulos H, Mir S (2012) Adaptive alternate analog test. IEEE Des Test Comput 29(4):71\u201379","journal-title":"IEEE Des Test Comput"},{"key":"6117_CR155","doi-asserted-by":"crossref","unstructured":"Stratigopoulos H, Mir S, Acar E, Ozev S (2009) Defect filter for alternate RF test. In Proc. 14th IEEE European Test Symposium, pp. 101\u2013106","DOI":"10.1109\/ETS.2009.32"},{"key":"6117_CR156","doi-asserted-by":"crossref","unstructured":"Stratigopoulos H, Mir S, Makris Y (2009) Enrichment of limited training sets in machine-learning-based analog\/RF test. In Proc. Design, Automation & Test in Europe Conference & Exhibition, pp. 1668\u20131673","DOI":"10.1109\/DATE.2009.5090931"},{"issue":"12","key":"6117_CR157","doi-asserted-by":"publisher","first-page":"1977","DOI":"10.1109\/TCAD.2014.2360458","volume":"33","author":"H Stratigopoulos","year":"2014","unstructured":"Stratigopoulos H, Sunter S (2014) Fast Monte Carlo-based estimation of analog parametric test metrics. IEEE Trans Comput Aided Des Integr Circuits Syst 33(12):1977\u20131990","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR158","doi-asserted-by":"crossref","unstructured":"Sumikawa N, Nero M, Wang L (2017) Kernel based clustering for quality improvement and excursion detection. In Proc. IEEE International Test Conference (ITC), pp. 1\u201310","DOI":"10.1109\/TEST.2017.8242071"},{"key":"6117_CR159","doi-asserted-by":"crossref","unstructured":"Sun Y, Millican SK (2019) Test point insertion using artificial neural networks. In Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 253\u2013258","DOI":"10.1109\/ISVLSI.2019.00054"},{"issue":"4","key":"6117_CR160","doi-asserted-by":"publisher","first-page":"339","DOI":"10.1007\/s10836-022-06016-9","volume":"38","author":"Y Sun","year":"2022","unstructured":"Sun Y, Millican SK (2022) Applying artificial neural networks to logic built-in self-test: Improving test point insertion. J Electron Test Theory Appl 38(4):339\u2013352","journal-title":"J Electron Test Theory Appl"},{"key":"6117_CR161","doi-asserted-by":"crossref","unstructured":"Sun Y, Millican SK, Agrawal VD (2020) Special session: Survey of test point insertion for logic built-in self-test. In Proc. IEEE 38th VLSI Test Symposium (VTS), pp. 1\u20136","DOI":"10.1109\/VTS48691.2020.9107584"},{"key":"6117_CR162","doi-asserted-by":"crossref","unstructured":"Sun Z, Jiang L, Xu Q, Zhang Z, Wang Z, Gu X (2013) AgentDiag: An agent-assisted diagnostic framework for board-level functional failures. In Proc. IEEE International Test Conference (ITC), pp. 1\u20138","DOI":"10.1109\/TEST.2013.6651918"},{"key":"6117_CR163","doi-asserted-by":"crossref","unstructured":"Sun Z, Jiang L, Xu Q, Zhang Z, Wang Z, Gu X (2015) On test syndrome merging for reasoning-based board-level functional fault diagnosis. In Proc. 20th Asia and South Pacific Design Automation Conference, pp. 737\u2013742","DOI":"10.1109\/ASPDAC.2015.7059098"},{"key":"6117_CR164","doi-asserted-by":"crossref","unstructured":"Tafertshofer P, Ganz A, Henftling M (1997) A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), pp. 648\u2013655","DOI":"10.1109\/ICCAD.1997.643607"},{"key":"6117_CR165","unstructured":"Tan SC, Ting KM, Liu TF (2011) Fast anomaly detection for streaming data. IJCAI\u201911, AAAI Press, p. 1511-1516"},{"key":"6117_CR166","doi-asserted-by":"crossref","unstructured":"Tang H, Manish S, Rajski J, Keim M, Benware B (2007) Analyzing volume diagnosis results with statistical learning for yield improvement. In Proc. 12th IEEE European Test Symposium (ETS\u201907), pp. 145\u2013150","DOI":"10.1109\/ETS.2007.11"},{"issue":"2","key":"6117_CR167","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1109\/MDT.2010.52","volume":"27","author":"M Tehranipoor","year":"2010","unstructured":"Tehranipoor M, Butler KM (2010) Power supply noise: A survey on effects and research. IEEE Des Test Comput 27(2):51\u201367","journal-title":"IEEE Des Test Comput"},{"key":"6117_CR168","doi-asserted-by":"crossref","unstructured":"Tipping ME (2004) Bayesian inference: An introduction to principles and practice in machine learning, pp. 41\u201362. Berlin, Heidelberg: Springer Berlin Heidelberg","DOI":"10.1007\/978-3-540-28650-9_3"},{"issue":"7","key":"6117_CR169","doi-asserted-by":"publisher","first-page":"1470","DOI":"10.1109\/TIM.2008.917196","volume":"57","author":"A Valdes-Garcia","year":"2008","unstructured":"Valdes-Garcia A, Venkatasubramanian R, Silva-Martinez J, Sanchez-Sinencio E (2008) A broadband CMOS amplitude detector for on-chip RF measurements. IEEE Trans Instrum Meas 57(7):1470\u20131477","journal-title":"IEEE Trans Instrum Meas"},{"issue":"5","key":"6117_CR170","doi-asserted-by":"publisher","first-page":"1018","DOI":"10.1109\/TCSI.2007.895531","volume":"54","author":"R Voorakaranam","year":"2007","unstructured":"Voorakaranam R, Akbay SS, Bhattacharya S, Cherubal S, Chatterjee A (2007) Signature testing of analog and RF circuits: Algorithms and methodology. IEEE Trans Circuits Syst I Regul Pap 54(5):1018\u20131031","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"6117_CR171","doi-asserted-by":"crossref","unstructured":"Wang H, Poku O, Yu X, Liu S, Komara I, Blanton RD (2012) Test-data volume optimization for diagnosis. In Proc. Design Automation Conference, pp. 567\u2013572","DOI":"10.1145\/2228360.2228462"},{"key":"6117_CR172","doi-asserted-by":"crossref","unstructured":"Wang J, Walker DMH, Majhi A, Kruseman B, Gronthoud G, Villagra LE, van de Wiel P, Eichenberger S (2006) Power supply noise in delay testing. In Proc. IEEE International Test Conference, pp. 1\u201310","DOI":"10.1109\/TEST.2006.297642"},{"key":"6117_CR173","unstructured":"Wang S, Wei W (2009) Machine learning-based volume diagnosis. In Proc. Design, Automation & Test in Europe Conference & Exhibition, pp. 902\u2013905"},{"key":"6117_CR174","unstructured":"Wen X, Yamashita Y, Kajihara S, Wang LT, Saluja KK, Kinoshita K (2005) On low-capture-power test generation for scan testing. In Proc. 23rd IEEE VLSI Test Symposium (VTS), pp. 265\u2013270"},{"issue":"2","key":"6117_CR175","doi-asserted-by":"publisher","first-page":"222","DOI":"10.1109\/TCAD.1987.1270266","volume":"6","author":"CL Wey","year":"1987","unstructured":"Wey CL, Lombardi F (1987) On the repair of redundant RAM\u2019s. IEEE Trans Comput Aided Des Integr Circuits Syst 6(2):222\u2013231","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR176","doi-asserted-by":"crossref","unstructured":"Xanthopoulos C, Sarson P, Reiter H, Makris Y (2017) Automated die inking: A pattern recognition-based approach. In Proc. IEEE International Test Conference (ITC), pp. 1\u20136","DOI":"10.1109\/TEST.2017.8242040"},{"issue":"1","key":"6117_CR177","doi-asserted-by":"publisher","first-page":"141","DOI":"10.1007\/s10836-021-05925-5","volume":"37","author":"Y Xiao","year":"2021","unstructured":"Xiao Y, Huang X, Liu K (2021) Model transferability from imagenet to lithography hotspot detection. J Electronic Testing Theory Applications 37(1):141\u2013149","journal-title":"J Electronic Testing Theory Applications"},{"key":"6117_CR178","doi-asserted-by":"crossref","unstructured":"Xue Y, Poku O, Li X, Blanton RD (2013) PADRE: Physically-aware diagnostic resolution enhancement. In Proc. IEEE International Test Conference (ITC), pp. 1\u201310","DOI":"10.1109\/TEST.2013.6651899"},{"key":"6117_CR179","doi-asserted-by":"crossref","unstructured":"Ye F, Firouzi F, Yang Y, Chakrabarty K, Tahoori MB (2014) On-chip voltage-droop prediction using support-vector machines. In Proc. IEEE 32nd VLSI Test Symposium (VTS), pp. 1\u20136","DOI":"10.1109\/VTS.2014.6818798"},{"issue":"5","key":"6117_CR180","doi-asserted-by":"publisher","first-page":"723","DOI":"10.1109\/TCAD.2012.2234827","volume":"32","author":"F Ye","year":"2013","unstructured":"Ye F, Zhang Z, Chakrabarty K, Gu X (2013) Board-level functional fault diagnosis using artificial neural networks, support-vector machines, and weighted-majority voting. IEEE Trans Comput Aided Des Integr Circuits Syst 32(5):723\u2013736","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"2","key":"6117_CR181","doi-asserted-by":"publisher","first-page":"279","DOI":"10.1109\/TCAD.2013.2287184","volume":"33","author":"F Ye","year":"2014","unstructured":"Ye F, Zhang Z, Chakrabarty K, Gu X (2014) Board-level functional fault diagnosis using multikernel support vector machines and incremental learning. IEEE Trans Comput Aided Des Integr Circuits Syst 33(2):279\u2013290","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6117_CR182","doi-asserted-by":"crossref","unstructured":"Zhang W, Goh AT (2016) Multivariate adaptive regression splines and neural network models for prediction of pile drivability. Geoscience Frontiers 7(1)45\u201352. Special Issue: Progress of Machine Learning in Geosciences","DOI":"10.1016\/j.gsf.2014.10.003"},{"key":"6117_CR183","doi-asserted-by":"crossref","unstructured":"Zhang Y, Agrawal VD (2010) A diagnostic test generation system. In Proc. IEEE International Test Conference (ITC), pp. 12.3.1\u201312.3.9","DOI":"10.1109\/TEST.2010.5699237"},{"key":"6117_CR184","doi-asserted-by":"crossref","unstructured":"Zhang Z, Chakrabarty K, Wang Z, Wang Z, Gu X (2011) Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks. In Proc. International Test Conference, pp. 1\u20139","DOI":"10.1109\/TEST.2011.6139139"},{"key":"6117_CR185","doi-asserted-by":"crossref","unstructured":"Zhang Z, Gu X, Xie Y, Wang Z, Wang Z, Chakrabarty K (2012) Diagnostic system based on support-vector machines for board-level functional diagnosis. In Proc. 17th IEEE European Test Symposium (ETS), pp. 1\u20136","DOI":"10.1109\/ETS.2012.6233029"},{"key":"6117_CR186","doi-asserted-by":"crossref","unstructured":"Zhou Z, Guin U, Li P, Agrawal VD (2021) Defect characterization and testing of skyrmion-based logic circuits. In Proc. IEEE VLSI Test Symp. (VTS\u201921), (USA), pp. 1\u20137","DOI":"10.1109\/VTS50974.2021.9441054"},{"key":"6117_CR187","doi-asserted-by":"crossref","unstructured":"Zhou Z, Guin U, Li P, Agrawal VD (2022) Fault modeling and test generation for technology-specific defects of skyrmion logic circuits. In Proc. IEEE VLSI Test Symp. (VTS\u201922), (USA), pp. 1\u20137","DOI":"10.1109\/VTS52500.2021.9794254"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-024-06117-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-024-06117-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-024-06117-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,16]],"date-time":"2024-11-16T07:11:01Z","timestamp":1731741061000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-024-06117-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4]]},"references-count":187,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2024,4]]}},"alternative-id":["6117"],"URL":"https:\/\/doi.org\/10.1007\/s10836-024-06117-7","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2024,4]]},"assertion":[{"value":"20 November 2023","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 March 2024","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 April 2024","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"We declare that we have no financial and personal relationships with other people or organizations that can inappropriately influence our work, there is no professional or other personal interest of any nature or kind in any product, service and\/or company that could be construed as influencing the position presented in, or the review of, the manuscript entitled. Also, one of our co-authors is an editor of the journal.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of Interest"}}]}}