{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:39:30Z","timestamp":1740123570921,"version":"3.37.3"},"reference-count":55,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2024,6]]},"DOI":"10.1007\/s10836-024-06124-8","type":"journal-article","created":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T19:02:15Z","timestamp":1719860535000},"page":"315-328","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Design and Verification of a SAR ADC SystemVerilog Real Number Model"],"prefix":"10.1007","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2044-4453","authenticated-orcid":false,"given":"Nikolaos","family":"Georgoulopoulos","sequence":"first","affiliation":[]},{"given":"Theodora","family":"Mamali","sequence":"additional","affiliation":[]},{"given":"Alkis","family":"Hatzopoulos","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,7,1]]},"reference":[{"key":"6124_CR1","unstructured":"Accelera\u00a0(2011) Universal Verification Methodology (UVM) 1.1 User\u2019s Guide, https:\/\/accellera.org\/, (Accessed 10 Aug 2021)"},{"key":"6124_CR2","unstructured":"Balasubramanian S, Hardee P (2013) Solutions for Mixed Signal SoC Verification Using Real Number Models. Cadence Design Systems. https:\/\/www.cadence.com\/. (Accessed 10 Aug 2021)"},{"key":"6124_CR3","unstructured":"Hartong W, Cranston S (2009) Real Valued Modeling for Mixed Signal Simulation, Cadence Design Systems"},{"key":"6124_CR4","unstructured":"Vogelsong R, Osman AH, Mohamed M (2015) Practical RNM with SystemVerilog. Proc. CDNLive 2015"},{"key":"6124_CR5","doi-asserted-by":"publisher","first-page":"647","DOI":"10.1007\/s10836-013-5409-5","volume":"29","author":"N Bombieri","year":"2013","unstructured":"Bombieri N, Ebeid E, Fummi F et al (2013) On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation. J Electron Test 29:647\u2013667","journal-title":"J Electron Test"},{"key":"6124_CR6","unstructured":"Chen J, Henrie M (2012) Mixed-Signal Methodology Guide, Lulu, https:\/\/www.lulu.com\/, (Accessed 10 Aug 2021)"},{"key":"6124_CR7","doi-asserted-by":"publisher","unstructured":"Cross D (2023) Real Valued Models for Verification of Silicon Photonic Systems\u201d, Proc. (2023) IEEE Photonics Conference (IPC). Orlando, FL, USA 1\u20132.\u00a0https:\/\/doi.org\/10.1109\/IPC57732.2023.10360544","DOI":"10.1109\/IPC57732.2023.10360544"},{"key":"6124_CR8","doi-asserted-by":"publisher","first-page":"685","DOI":"10.1007\/s10836-021-05977-7","volume":"37","author":"N Georgoulopoulos","year":"2021","unstructured":"Georgoulopoulos N, Hatzopoulos A (2021) Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog. J Electron Test 37:685\u2013700","journal-title":"J Electron Test"},{"key":"6124_CR9","doi-asserted-by":"publisher","first-page":"79721","DOI":"10.1109\/ACCESS.2023.3299227","volume":"11","author":"M Maurice","year":"2023","unstructured":"Maurice M, Dessouky M, Salem A (2023) Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator. IEEE Access 11:79721\u201379738. https:\/\/doi.org\/10.1109\/ACCESS.2023.3299227","journal-title":"IEEE Access"},{"key":"6124_CR10","doi-asserted-by":"publisher","unstructured":"Barros JS, Schulz VH, Lettnin DV (2018) An Adaptive Closed-Loop Verification Approach in UVM-SystemC for AMS Circuits\u201d, Proc. DV (2018) 31st Symposium on Integrated Circuits and Systems Design (SBCCI). Bento Gon\u00e7alves, Brazil 1\u20136.\u00a0https:\/\/doi.org\/10.1109\/SBCCI.2018.8533229","DOI":"10.1109\/SBCCI.2018.8533229"},{"key":"6124_CR11","doi-asserted-by":"publisher","unstructured":"Biswal BP, Singh\u00a0A, Singh B (2017) Cache coherency controller verification IP using SystemVerilog Assertions (SVA) and Universal Verification Methodologies (UVM),. Proc. 2017 11th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, India, pp. 21\u201324. https:\/\/doi.org\/10.1109\/ISCO.2017.7855984","DOI":"10.1109\/ISCO.2017.7855984"},{"key":"6124_CR12","doi-asserted-by":"publisher","unstructured":"Deepak R, Parvathy SJ, Arya S, Babu V (2020) Regression Based Mixed Signal Verification of an Ambient Light Sensor Interface\u201d, (2020) IEEE International Symposium on Circuits and Systems (ISCAS). Seville, Spain 1\u20134.\u00a0https:\/\/doi.org\/10.1109\/ISCAS45731.2020.9181161","DOI":"10.1109\/ISCAS45731.2020.9181161"},{"key":"6124_CR13","doi-asserted-by":"publisher","unstructured":"Dharani M, Bharathi M, Padmaja\u00a0N, Praveena K (2023) Design and Verification process of Combinational Adder using UVM Methodology. Proc. 2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS), Bangalore, India, pp. 359\u2013362.\u00a0https:\/\/doi.org\/10.1109\/ICAECIS58353.2023.10170273","DOI":"10.1109\/ICAECIS58353.2023.10170273"},{"key":"6124_CR14","doi-asserted-by":"publisher","unstructured":"Doshi NK, Suryawanshi\u00a0S, Kumar GN (2016) Development of generic verification environment based on UVM with case study on HMC controller. Proc. 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, pp. 550\u2013553.\u00a0https:\/\/doi.org\/10.1109\/RTEICT.2016.7807882","DOI":"10.1109\/RTEICT.2016.7807882"},{"key":"6124_CR15","doi-asserted-by":"publisher","unstructured":"Fu Y, Huang K, Zhang L, Liu F (2020) A System Function Verification Flow For Mixed-signal SoC\u201d, Proc. F (2020) 7th International Forum on Electrical Engineering and Automation (IFEEA). Hefei, China 738\u2013741.\u00a0https:\/\/doi.org\/10.1109\/IFEEA51475.2020.00157","DOI":"10.1109\/IFEEA51475.2020.00157"},{"key":"6124_CR16","doi-asserted-by":"crossref","unstructured":"Gayathri M (2016) A SV-UVM framework for Verification of SGMII IP Core with reusable AXI to WB Bridge UVC, Proc. 3rd International Conference on Advanced Computing and Communication Systems, ICACCS","DOI":"10.1109\/ICACCS.2016.7586315"},{"key":"6124_CR17","doi-asserted-by":"crossref","unstructured":"Khalifa K (2017) Extendable Generic Base Verification Architecture for Flash Memory Controllers Based on UVM, Proc. IEEE 21st International Conference on Computer Supported Cooperative Work in Design, CSCWD","DOI":"10.1109\/CSCWD.2017.8066759"},{"issue":"1","key":"6124_CR18","doi-asserted-by":"publisher","first-page":"193","DOI":"10.1109\/TVLSI.2018.2873387","volume":"27","author":"BC Lim","year":"2019","unstructured":"Lim BC, Horowitz M (2019) An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. IEEE Trans Very Large Scale Integr (VLSI) Syst 27(1):193\u2013204. https:\/\/doi.org\/10.1109\/TVLSI.2018.2873387","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"6124_CR19","doi-asserted-by":"crossref","unstructured":"Salah K (2014) A UVM-Based Smart Functional Verification Platform: Concepts, Pros, Cons, and Opportunities, Proc. 9th International Design and Test Symposium, DTS","DOI":"10.1109\/IDT.2014.7038594"},{"key":"6124_CR20","doi-asserted-by":"publisher","unstructured":"Zivkovic VA, Palazzi M, ChuenAlvan Lam\u00a0M, Isager M (2022) AMS Test Vector Generation using AMS Verification and IEEE P1687.2. Proc. 2022 IEEE European Test Symposium (ETS), Barcelona, Spain, pp. 1-4. https:\/\/doi.org\/10.1109\/ETS54262.2022.9810471","DOI":"10.1109\/ETS54262.2022.9810471"},{"issue":"3","key":"6124_CR21","doi-asserted-by":"publisher","first-page":"85","DOI":"10.14257\/ijunesst.2014.7.3.09","volume":"8","author":"S Hanfoug","year":"2014","unstructured":"Hanfoug S, Bouguechal NE, Barra S (2014) Behavioral non-ideal Model of 8-bit Current-Mode Successive Approximation Registers ADC by using Simulink, Proc. Int J\u00a0u- and e-Service, Sci Tech 8(3):85\u2013102","journal-title":"Int J\u00a0u- and e-Service, Sci Tech"},{"key":"6124_CR22","doi-asserted-by":"crossref","unstructured":"Santhanalakshmi M, Yasoda K (2015) Verilog-A implementation of energy-efficient SAR ADCs for biomedical application, Proc. 19th International Symposium on VLSI Design and Test, VDAT","DOI":"10.1109\/ISVDAT.2015.7208139"},{"key":"6124_CR23","unstructured":"Carsten W (2013) Method of modeling analog circuits in verilog for mixed-signal design simulations, Proc. 2013 European Conference on Circuit Theory and Design, ECCTD"},{"key":"6124_CR24","doi-asserted-by":"crossref","unstructured":"Georgoulopoulos N, Hatzopoulos A (2018) Efficiency Evaluation of a SystemVerilog-based Real Number Model, Proc. 7th International Conference on Modern Circuits and Systems Technologies, MOCAST","DOI":"10.1109\/MOCAST.2018.8376642"},{"key":"6124_CR25","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1007\/s10836-009-5137-z","volume":"26","author":"R Narayanan","year":"2010","unstructured":"Narayanan R, Zaki MH, Tahar S (2010) Using Stochastic Differential Equation for Verification of Noise in Analog\/RF Circuits. J Electron Test 26:97\u2013109","journal-title":"J Electron Test"},{"key":"6124_CR26","doi-asserted-by":"crossref","unstructured":"Subrahmaniyan Radhakrishnan S, Ozev S (2011) Adaptive Modeling of Analog\/RF Circuits for Efficient Fault Response Evaluation. J Electron Test 27:465\u2013476","DOI":"10.1007\/s10836-011-5221-z"},{"key":"6124_CR27","unstructured":"Aisola R et al (1996) Verilog-A Language Reference Manual, Open Verilog International, OVI"},{"key":"6124_CR28","doi-asserted-by":"publisher","unstructured":"Belay YA, Cabrini\u00a0A, Torelli G (2016) A comprehensive Verilog-A behavioral model of Spin-Transfer Torque memory cell,\u201d Proc. 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Lisbon, Portugal, pp. 1\u20134.\u00a0https:\/\/doi.org\/10.1109\/PRIME.2016.7519522","DOI":"10.1109\/PRIME.2016.7519522"},{"key":"6124_CR29","unstructured":"Chandrasekaran S et al (2009) Verilog-AMS Language Reference Manual, Accellera, https:\/\/www.accellera.org\/, (Accessed 10 Aug 2021)"},{"key":"6124_CR30","unstructured":"FitzPatrick D, Miller I (2003) Analog Behavioral Modeling with the Verilog-A Language, Kluwer Academic Publishers"},{"key":"6124_CR31","doi-asserted-by":"publisher","unstructured":"Jimenez-Dominguez E, Gonzalez-Diaz\u00a0VR, Rodriguez-Dominguez AM (2016) Behavioral model of a VCO varying its Kvco with Verilog-A,\u201d Proc. 13th International Conference on Power Electronics (CIEP), Guanajuato, Mexico, pp. 70\u201374.\u00a0https:\/\/doi.org\/10.1109\/CIEP.2016.7530733","DOI":"10.1109\/CIEP.2016.7530733"},{"key":"6124_CR32","doi-asserted-by":"publisher","unstructured":"Kuo\u00a0P-Y, Sie L-F (2015) Analyze the behavior model based on Verilog-A for Sallen-Key low-pass filter. Proc. 2015 IEEE International Conference on Consumer Electronics - Taiwan, Taipei, Taiwan, pp. 460\u2013461. https:\/\/doi.org\/10.1109\/ICCE-TW.2015.7216998","DOI":"10.1109\/ICCE-TW.2015.7216998"},{"key":"6124_CR33","doi-asserted-by":"publisher","unstructured":"Lena D, Grosso M, Bocca A, Macii\u00a0A, Rinaudo S (2016) A compact IGBT electro-thermal model in Verilog-A for fast system-level simulation. Proc. IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy, pp. 3793\u20133798.\u00a0https:\/\/doi.org\/10.1109\/IECON.2016.7793376","DOI":"10.1109\/IECON.2016.7793376"},{"key":"6124_CR34","unstructured":"Cadence Design Systems (2015) Verilog-AMS Real Valued Modeling Guide"},{"key":"6124_CR35","unstructured":"Cheng K-H, Jou CF (2003) 2.4 GHz CMOS VCO design with Verilog-AMS, Proceedings of the 12th International Conference on Fuzzy Systems, FUZZ"},{"key":"6124_CR36","unstructured":"Cundert KS, Zinke O (2004) The Designer\u2019s Guide to Verilog AMS, Kluwer Academic Publishers"},{"key":"6124_CR37","doi-asserted-by":"publisher","unstructured":"Hujer M, Manasek R, O'Mahony J, Feerick P, Barry\u00a0M, Walsh B (2006) Nanometer Wireless Transceiver Modeling using Verilog-AMS and SystemC. Proc. IEEE International Behavioral Modeling and Simulation Workshop, San Jose, CA, USA, pp. 150\u2013155.\u00a0https:\/\/doi.org\/10.1109\/BMAS.2006.283486","DOI":"10.1109\/BMAS.2006.283486"},{"issue":"3","key":"6124_CR38","doi-asserted-by":"publisher","first-page":"680","DOI":"10.1109\/TCSI.2014.2377411","volume":"62","author":"A Jakobsson","year":"2015","unstructured":"Jakobsson A, Serban A, Gong S (2015) Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS. IEEE Trans Circuits Syst I Regul Pap 62(3):680\u2013688. https:\/\/doi.org\/10.1109\/TCSI.2014.2377411","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"6124_CR39","doi-asserted-by":"publisher","unstructured":"Lian-xi L, Yin-tang Y, Zhang-ming\u00a0Z, Yani L (2005) Design of PLL system based Verilog-AMS behavior models,\u201d Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005., Suzhou, China, pp. 67\u201370.\u00a0https:\/\/doi.org\/10.1109\/IWVDVT.2005.1504466","DOI":"10.1109\/IWVDVT.2005.1504466"},{"key":"6124_CR40","doi-asserted-by":"publisher","first-page":"7","DOI":"10.1023\/A:1008329031457","volume":"13","author":"NJ Godambe","year":"1998","unstructured":"Godambe NJ, Richard Shi CJ (1998) \u201cBehavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.\u201d J Electron Test 13:7\u201317","journal-title":"J Electron Test"},{"key":"6124_CR41","unstructured":"Hern\u00e1ndez FAI, Canesin CA (2012) Electrical Power Distribution System modeling with VHDL-AMS for the construction of a Real-Time Digital Simulator using FPGAS devices, Proc. 10th IEEE International Conference on Industry Applications, IAS"},{"issue":"2","key":"6124_CR42","doi-asserted-by":"publisher","first-page":"204","DOI":"10.1109\/TCAD.2004.841071","volume":"24","author":"F Pecheux","year":"2005","unstructured":"Pecheux F, Lallement C, Vachoux A (2005) VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. IEEE Trans Comput Aided Des Integr Circuits Syst 24(2):204\u2013225. https:\/\/doi.org\/10.1109\/TCAD.2004.841071","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6124_CR43","doi-asserted-by":"publisher","unstructured":"Szermer M, Daniel\u00a0M, Napieralski A (2003) Modeling and simulation sigma-delta analog to digital converters using VHDL-AMS,\u201d The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., Slavske, Ukraine, pp. 331\u2013333.\u00a0https:\/\/doi.org\/10.1109\/CADSM.2003.1255082","DOI":"10.1109\/CADSM.2003.1255082"},{"key":"6124_CR44","doi-asserted-by":"crossref","unstructured":"Georgoulopoulos N, Hatzopoulos A (2017) Real number modeling of a flash ADC using SystemVerilog, Proc. Panhellenic Conference on Electronics and Telecommunications, PACET","DOI":"10.1109\/PACET.2017.8259969"},{"key":"6124_CR45","doi-asserted-by":"publisher","unstructured":"Lotfy A, Farooq SFS, Wang QS, Yaldiz S, Mosalikanti P, Kurd N (2015) A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology\u201d, Proc. (2015) IEEE Custom Integrated Circuits Conference (CICC). San Jose, CA, USA 1\u20134.\u00a0https:\/\/doi.org\/10.1109\/CICC.2015.7338432","DOI":"10.1109\/CICC.2015.7338432"},{"key":"6124_CR46","doi-asserted-by":"crossref","unstructured":"Shera E, Wegener C (2015) Buck converter modeling in SystemVerilog for verification and virtual test applications, Proc. IEEE 20th International Mixed-Signals Testing Workshop, IMSTW","DOI":"10.1109\/IMS3TW.2015.7177865"},{"key":"6124_CR47","doi-asserted-by":"publisher","unstructured":"Yang X, Niu X, Fan\u00a0J, Choi C (2013) Mixed-signal System-on-a-Chip (SoC) verification based on SystemVerilog model. Proc. 45th Southeastern Symposium on System Theory, Waco, TX, USA, pp. 17\u201321. https:\/\/doi.org\/10.1109\/SSST.2013.6524952","DOI":"10.1109\/SSST.2013.6524952"},{"key":"6124_CR48","unstructured":"Bromley J (2013) If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language, Proceedings of the 2013 Forum on specification and Design Languages, FDL"},{"key":"6124_CR49","doi-asserted-by":"publisher","unstructured":"Georgoulopoulos N, Giannou\u00a0I, Hatzopoulos A (2018) UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. Proc. 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Platja d'Aro, Spain, pp. 97\u2013102. https:\/\/doi.org\/10.1109\/PATMOS.2018.8464148","DOI":"10.1109\/PATMOS.2018.8464148"},{"key":"6124_CR50","doi-asserted-by":"publisher","unstructured":"Simon S, Bhat D, Rath A, Kirscher\u00a0J, Maurer L (2017) Coverage-driven mixed-signal verification of smart power ICs in a UVM environment,\u201d Proc. 22nd IEEE European Test Symposium (ETS), Limassol, Cyprus, pp. 1\u20136.\u00a0https:\/\/doi.org\/10.1109\/ETS.2017.7968237","DOI":"10.1109\/ETS.2017.7968237"},{"key":"6124_CR51","doi-asserted-by":"publisher","unstructured":"Simon S, Karaca \u00d6, Kirscher J, Rath A, Pelz\u00a0G, Maurer L (2016) Safety-oriented mixed-signal verification of automotive power devices in a UVM environment. Proc. 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, Portugal, pp. 1\u20134.\u00a0https:\/\/doi.org\/10.1109\/SMACD.2016.7520718","DOI":"10.1109\/SMACD.2016.7520718"},{"key":"6124_CR52","doi-asserted-by":"publisher","unstructured":"Yun Y-N, Kim J-B, Kim N-D, Min B (2011) Beyond UVM for practical SoC verification. Proc. B 2011 International SoC Design Conference, Jeju. Korea (South) 158\u2013162.\u00a0https:\/\/doi.org\/10.1109\/ISOCC.2011.6138671","DOI":"10.1109\/ISOCC.2011.6138671"},{"key":"6124_CR53","doi-asserted-by":"crossref","unstructured":"Nicollini G, Confalonieri P, Senderowicz D (1989) A fully differential sample-and-hold circuit for high-speed applications. IEEE J Solid-State Circuits JSSC","DOI":"10.1109\/JSSC.1989.572640"},{"key":"6124_CR54","doi-asserted-by":"crossref","unstructured":"Tay TT, Mareels I, Moore JB (1998) High performance control.\u00a0https:\/\/www.researchgate.net\/publication\/235683246_High_Performance_Control, pp 93","DOI":"10.1007\/978-1-4612-1786-2"},{"key":"6124_CR55","doi-asserted-by":"crossref","unstructured":"Moskala M, Kloczko P, Cieplucha M, Pleskacz W (2015) UVM-based verification of bluetooth low energy controlle. Proc. IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits Systems, DDECS","DOI":"10.1109\/DDECS.2015.48"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-024-06124-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-024-06124-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-024-06124-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T07:03:47Z","timestamp":1723705427000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-024-06124-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6]]},"references-count":55,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2024,6]]}},"alternative-id":["6124"],"URL":"https:\/\/doi.org\/10.1007\/s10836-024-06124-8","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2024,6]]},"assertion":[{"value":"29 November 2023","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"6 June 2024","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 July 2024","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}