{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T19:57:51Z","timestamp":1768075071913,"version":"3.49.0"},"reference-count":29,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62027815"],"award-info":[{"award-number":["62027815"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274052"],"award-info":[{"award-number":["62274052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62174048"],"award-info":[{"award-number":["62174048"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2024,6]]},"DOI":"10.1007\/s10836-024-06125-7","type":"journal-article","created":{"date-parts":[[2024,7,16]],"date-time":"2024-07-16T07:02:04Z","timestamp":1721113324000},"page":"405-415","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision"],"prefix":"10.1007","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-5846-608X","authenticated-orcid":false,"given":"Yuqi","family":"Pan","sequence":"first","affiliation":[]},{"given":"Huaguo","family":"Liang","sequence":"additional","affiliation":[]},{"given":"Junming","family":"Li","sequence":"additional","affiliation":[]},{"given":"Jinxing","family":"Qu","sequence":"additional","affiliation":[]},{"given":"Zhengfeng","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Maoxiang","family":"Yi","sequence":"additional","affiliation":[]},{"given":"Yingchun","family":"Lu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,7,16]]},"reference":[{"key":"6125_CR1","doi-asserted-by":"publisher","unstructured":"Ahmadi A, Nahar A, Orr B, Pas M, Makris Y (2016) Wafer-level process variation-driven probe-test flow selection for test cost reduction in Analog\/RF ICs. Proc IEEE VLSI Test Symp 1\u20136. https:\/\/doi.org\/10.1109\/VTS.2016.7477263","DOI":"10.1109\/VTS.2016.7477263"},{"key":"6125_CR2","doi-asserted-by":"publisher","unstructured":"El Badawi H, Azais F, Bernard S, Comte M, Kerzerho V, Lefevre F, Gorenflot I (2020) Implementing indirect test of RF circuits without compromising test quality: a practical case study. IEEE Latin-Am Test Symp LATS 1\u20136. https:\/\/doi.org\/10.1109\/LATS49555.2020.9093666","DOI":"10.1109\/LATS49555.2020.9093666"},{"issue":"2","key":"6125_CR3","doi-asserted-by":"publisher","first-page":"225","DOI":"10.1007\/s10836-021-05934-4","volume":"37","author":"E El Badawi","year":"2021","unstructured":"El Badawi E, Azais F, Bernard S, Comte V, Kerzerho V, Lefevre F (2021) Evaluation of a two-tier adaptive indirect test flow for a front-end RF circuit. J Electron Test-Theory Appl 37(2):225\u2013242. https:\/\/doi.org\/10.1007\/s10836-021-05934-4","journal-title":"J Electron Test-Theory Appl"},{"key":"6125_CR4","doi-asserted-by":"publisher","unstructured":"Gon\u00e7alves H, Li X, Correia M, Tavares V, Carulli J, Butler K (2015) A fast spatial variation modeling algorithm for efficient test cost reduction of analog\/RF circuits. Proc Des Autom Test Eur DATE 1042\u20131047. https:\/\/doi.org\/10.7873\/DATE.2015.0690","DOI":"10.7873\/DATE.2015.0690"},{"key":"6125_CR5","doi-asserted-by":"publisher","unstructured":"Herrera AEH, Stoyanov S, Bailey C, Walshaw C, Yin C (2019) Data analytics to reduce stop-on-fail test in electronics manufacturing. Open Computer Science 9. https:\/\/doi.org\/10.1515\/comp-2019-0014","DOI":"10.1515\/comp-2019-0014"},{"key":"6125_CR6","doi-asserted-by":"publisher","unstructured":"Huang K, Kupp N, Carulli JM, Makris Y (2013) On combining alternate test with spatial correlation modeling in Analog\/RF ICs. Proc European Test Workshop 1\u20136. https:\/\/doi.org\/10.1109\/ETS.2013.6569358","DOI":"10.1109\/ETS.2013.6569358"},{"issue":"11","key":"6125_CR7","doi-asserted-by":"publisher","first-page":"53","DOI":"10.1109\/MDAT.2014.2361721","volume":"32","author":"K Huang","year":"2015","unstructured":"Huang K, Kupp N, Xanthopoulos C, Carulli JM, Makris Y (2015) Low-cost Analog\/RF IC testing through combined intra- and inter-die correlation models. IEEE Des Test 32(11):53\u201360. https:\/\/doi.org\/10.1109\/MDAT.2014.2361721","journal-title":"IEEE Des Test"},{"key":"6125_CR8","doi-asserted-by":"publisher","unstructured":"Hinojosa A, Stoyanov S (2018) Data driven predictive model to compact a production stop-on-fail test set for an electronic device. Proc - Int Conf Comput Electron Commun Eng iCCECE 59\u201364. https:\/\/doi.org\/10.1109\/iCCECOME.2018.8658941","DOI":"10.1109\/iCCECOME.2018.8658941"},{"key":"6125_CR9","doi-asserted-by":"publisher","unstructured":"Hsu CK, Lin F, Cheng KT, Zhang WY, Li X, Carulli JM, Butler KM (2013) Test data analytics - exploring spatial and test-item correlations in production test data. Proc IEEE Int Test Conf (ITC) 1\u201310. https:\/\/doi.org\/10.1109\/TEST.2013.6651900","DOI":"10.1109\/TEST.2013.6651900"},{"key":"6125_CR10","doi-asserted-by":"publisher","unstructured":"Hsu CK, Sarson P, Schatzberger G, Leisenberger F, Carulli J, Siddhartha S, Cheng KT (2016) Variation and failure characterization through pattern classification of test data from multiple test stages. Proc IEEE Int Test Conf (ITC) 1\u201310. https:\/\/doi.org\/10.1109\/TEST.2016.7805845","DOI":"10.1109\/TEST.2016.7805845"},{"issue":"3","key":"6125_CR11","doi-asserted-by":"publisher","first-page":"431","DOI":"10.1109\/tsm.2015.2443864","volume":"28","author":"S Kang","year":"2015","unstructured":"Kang S, Cho S, An D, Rim J (2015) Using wafer map features to better predict die-level failures in final test. IEEE Trans Semicond Manuf 28(3):431\u2013437. https:\/\/doi.org\/10.1109\/tsm.2015.2443864","journal-title":"IEEE Trans Semicond Manuf"},{"issue":"3","key":"6125_CR12","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/mdt.2012.2206552","volume":"30","author":"S Krishnan","year":"2013","unstructured":"Krishnan S, Kerkhoff HG (2013) Exploiting multiple mahalanobis distance metrics to screen outliers from analog product manufacturing test responses. IEEE Des Test 30(3):18\u201324. https:\/\/doi.org\/10.1109\/mdt.2012.2206552","journal-title":"IEEE Des Test"},{"issue":"2","key":"6125_CR13","doi-asserted-by":"publisher","first-page":"372","DOI":"10.1109\/tsm.2022.3145855","volume":"35","author":"KSM Li","year":"2022","unstructured":"Li KSM, Chen LLY, Cheng KCC, Liao PYY, Wang SJ, Huang AYA, Chou L, Tsai NCY, Lee CS (2022) TestDNA-E: Wafer defect signature for pattern recognition by ensemble learning. IEEE Trans Semicond Manuf 35(2):372\u2013374. https:\/\/doi.org\/10.1109\/tsm.2022.3145855","journal-title":"IEEE Trans Semicond Manuf"},{"key":"6125_CR14","doi-asserted-by":"publisher","unstructured":"Liu MY, Chakrabarty K (2021) Adaptive methods for machine learning-based testing of integrated circuits and boards. Proc IEEE Int Test Conf (ITC) 153\u2013162. https:\/\/doi.org\/10.1109\/itc50571.2021.00023","DOI":"10.1109\/itc50571.2021.00023"},{"key":"6125_CR15","doi-asserted-by":"publisher","unstructured":"Neethirajan D, Niranjan VA, Willis R, Nahar A, Webster D, Makris Y (2022) Machine learning-based overkill reduction through inter-test correlation. Proc IEEE VLSI Test Symp 1\u20137. https:\/\/doi.org\/10.1109\/vts52500.2021.9794170","DOI":"10.1109\/vts52500.2021.9794170"},{"issue":"2","key":"6125_CR16","doi-asserted-by":"publisher","first-page":"386","DOI":"10.1109\/tcad.2020.2994257","volume":"40","author":"RJ Pan","year":"2021","unstructured":"Pan RJ, Zhang ZB, Li X, Chakrabarty X, Gu L (2021) Black-box test-cost reduction based on bayesian network models. IEEE Trans Comput-Aided Design Integr Circuits Syst 40(2):386\u2013399. https:\/\/doi.org\/10.1109\/tcad.2020.2994257","journal-title":"IEEE Trans Comput-Aided Design Integr Circuits Syst"},{"key":"6125_CR17","doi-asserted-by":"publisher","unstructured":"Shintani M, Mian RUH, Inoue M, Nakamura T, Kajiyama M, Eiki M (2021) Wafer-level variation modeling for multi-site RF IC testing via hierarchical gaussian process. Proc IEEE Int Test Conf (ITC) 103\u2013112. https:\/\/doi.org\/10.1109\/itc50571.2021.00018","DOI":"10.1109\/itc50571.2021.00018"},{"key":"6125_CR18","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/ETS.2018.8400701","volume-title":"Machine learning applications in IC testing","author":"HG Stratigopoulos","year":"2018","unstructured":"Stratigopoulos HG (2018) Machine learning applications in IC testing. European Test Workshop, Proc, pp 1\u201310. https:\/\/doi.org\/10.1109\/ETS.2018.8400701"},{"issue":"11","key":"6125_CR19","doi-asserted-by":"publisher","first-page":"1760","DOI":"10.1109\/TCAD.2005.855835","volume":"24","author":"HGD Stratigopoulos","year":"2005","unstructured":"Stratigopoulos HGD, Makris Y (2005) Non-linear decision boundaries for testing analog circuits, IEEE Trans. Comput-Aided Design Integr Circuits Sys 24(11):1760\u20131773. https:\/\/doi.org\/10.1109\/TCAD.2005.855835","journal-title":"Comput-Aided Design Integr Circuits Sys"},{"issue":"10","key":"6125_CR20","doi-asserted-by":"publisher","first-page":"2125","DOI":"10.1109\/tcad.2017.2783302","volume":"37","author":"HG Stratigopoulos","year":"2018","unstructured":"Stratigopoulos HG, Streitwieser C (2018) Adaptive test with test escape estimation for mixed-signal ICs. IEEE Trans Comput-Aided Design Integr Circuits Syst 37(10):2125\u20132138. https:\/\/doi.org\/10.1109\/tcad.2017.2783302","journal-title":"IEEE Trans Comput-Aided Design Integr Circuits Syst"},{"issue":"2","key":"6125_CR21","doi-asserted-by":"publisher","first-page":"315","DOI":"10.1109\/tsm.2018.2825482","volume":"31","author":"G Tello","year":"2018","unstructured":"Tello G, Al-Jarrah OY, Yoo PD, Al-Hammadi Y, Muhaidat S, Lee U (2018) Deep-structured machine learning model for the recognition of mixed-defect patterns in semiconductor fabrication processes. IEEE Trans Semicond Manuf 31(2):315\u2013322. https:\/\/doi.org\/10.1109\/tsm.2018.2825482","journal-title":"IEEE Trans Semicond Manuf"},{"key":"6125_CR22","doi-asserted-by":"publisher","unstructured":"Tsai TH, Lee YC, Hsieh CY (2019) Enhancing the data analysis in IC testing by machine learning techniques. Proc Tech Pap Int Microsystems Pack Assem Circuits Technol Conf IMPACT 183\u2013186. https:\/\/doi.org\/10.1109\/IMPACT47228.2019.9024981","DOI":"10.1109\/IMPACT47228.2019.9024981"},{"issue":"1","key":"6125_CR23","doi-asserted-by":"publisher","first-page":"104","DOI":"10.1109\/tsm.2018.2883763","volume":"32","author":"R Wang","year":"2019","unstructured":"Wang R, Zhang LM, Chen N (2019) Spatial correlated data monitoring in semiconductor manufacturing using gaussian process model. IEEE Trans Semicond Manuf 32(1):104\u2013111. https:\/\/doi.org\/10.1109\/tsm.2018.2883763","journal-title":"IEEE Trans Semicond Manuf"},{"issue":"2","key":"6125_CR24","doi-asserted-by":"publisher","first-page":"295","DOI":"10.1109\/tdmr.2020.2994291","volume":"20","author":"C Xanthopoulos","year":"2020","unstructured":"Xanthopoulos C, Neckermann A, List P, Tschernay KP, Sarson P, Makris Y (2020) Automated die inking. IEEE Trans Device Mater Reliab 20(2):295\u2013307. https:\/\/doi.org\/10.1109\/tdmr.2020.2994291","journal-title":"IEEE Trans Device Mater Reliab"},{"key":"6125_CR25","doi-asserted-by":"publisher","DOI":"10.1109\/vts50974.2021.9441055","author":"CH Yang","year":"2021","unstructured":"Yang CH, Yen CH, Wang TR, Chen CT, Chern M, Chen YY, Lee JN, Kao SY, Wu KC, Chao MCT (2021) Identifying good-dice-in-bad-neighborhoods using artificial neural networks. Proc IEEE VLSI Test Symp. https:\/\/doi.org\/10.1109\/vts50974.2021.9441055","journal-title":"Proc IEEE VLSI Test Symp"},{"issue":"6","key":"6125_CR26","doi-asserted-by":"publisher","first-page":"1116","DOI":"10.1109\/tvlsi.2012.2205027","volume":"21","author":"E Yilmaz","year":"2013","unstructured":"Yilmaz E, Ozev S, Butler KM (2013) Per-device adaptive test for Analog\/RF circuits using entropy-based process monitoring. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(6):1116\u20131128. https:\/\/doi.org\/10.1109\/tvlsi.2012.2205027","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"6125_CR27","doi-asserted-by":"publisher","unstructured":"Zhang JL, You HL, Jia RX (2019) Reliability hazard characterization of wafer-level spatial metrology parameters based on LOF-KNN method. Proc Int Symp Phys Failure Anal Integr Circuits IPFA 1\u20134. https:\/\/doi.org\/10.1109\/IPFA47161.2019.8984814","DOI":"10.1109\/IPFA47161.2019.8984814"},{"issue":"2","key":"6125_CR28","doi-asserted-by":"publisher","first-page":"266","DOI":"10.1109\/tsm.2022.3144283","volume":"35","author":"JL Zhang","year":"2022","unstructured":"Zhang JL, You HL, Jia RX, Wang XW (2022) The research on screening method to reduce chip test escapes by using multi-correlation analysis of parameters. IEEE Trans Semicond Manuf 35(2):266\u2013271. https:\/\/doi.org\/10.1109\/tsm.2022.3144283","journal-title":"IEEE Trans Semicond Manuf"},{"key":"6125_CR29","doi-asserted-by":"publisher","unstructured":"Zhang S, Li X, Blanton RD, da Silva JM, Carulli JM, Butler KM (2014) Bayesian model fusion: Enabling test cost reduction of analog\/RF circuits via wafer-level spatial variation modeling. Proc IEEE Int Test Conf (ITC) 1\u201310. https:\/\/doi.org\/10.1109\/TEST.2014.7035328","DOI":"10.1109\/TEST.2014.7035328"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-024-06125-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-024-06125-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-024-06125-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T07:03:59Z","timestamp":1723705439000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-024-06125-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6]]},"references-count":29,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2024,6]]}},"alternative-id":["6125"],"URL":"https:\/\/doi.org\/10.1007\/s10836-024-06125-7","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,6]]},"assertion":[{"value":"10 April 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"8 June 2024","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 July 2024","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing Interests"}}]}}